Zero-crossing detector for DC-DC converter systems and methods
Embodiments described herein provide a zero-crossing detector (ZCD) for a direct current to direct current (DC-DC) converter. The ZCD includes a ZCD integrator configured to receive a switch voltage and an output voltage of a power stage of the DC-DC converter and to generate a zero-crossing detect signal based, at least in part, on the received switch voltage and output voltage, where the zero-crossing detect signal is configured to indicate an output current in an output inductor of the power stage of the DC-DC converter is approximately zero. The ZCD may also include a ZCD offset calibrator configured to receive the switch voltage and generate a ZCD calibration offset based, at least in part, on the received switch voltage, where the ZCD integrator is configured to generate the zero-crossing detect signal based, at least in part, on the ZCD calibration offset.
1. A zero-crossing detector (ZCD) for a direct current to direct current (DC-DC) converter, the ZCD comprising:
a ZCD integrator including:
a differential voltage integrator configured to receive a switch voltage and an output voltage of a power stage of the DC-DC converter and to generate an integrator output based on the switch voltage and the output voltage o the power stage; and
an output comparator configured to generate a zero-crossing detect signal based, at least in part, on the integrator output and the output voltage of the power stage, wherein the zero-crossing detect signal indicates whether an output current in an output inductor of the power stage of the DC-DC converter is approximately zero.
2. The ZCD of claim 1 , wherein the ZCD integrator comprises:
an integrator reset switch configured to reset the differential voltage integrator during an idle mode of the DC-DC converter; and
a ZCD offset calibration applicator configured to receive the output voltage and a ZCD calibration offset and provide a corresponding calibrated output voltage to the output comparator, wherein the calibrated output voltage is configured to compensate for operational non-idealities associated with operation of the DC-DC converter.
3. The ZCD of claim 1 , further comprising:
a ZCD offset calibrator configured to receive the switch voltage and generate a ZCD calibration offset based, at least in part, on the received switch voltage;
wherein the ZCD integrator is configured to generate the zero-crossing detect signal based, at least in part, on the ZCD calibration offset.
4. The ZCD of claim 3 , wherein the ZCD offset calibrator comprises:
a current direction detector configured to receive the switch voltage, compare the switch voltage to a reference voltage for the DC-DC converter approximately when a low-side switch of the power stage transitions to an off state, and generate a current direction signal based, at least in part, on the comparison of the switch voltage and the reference voltage; and
a logic device configured to receive the current direction signal and generate the ZCD calibration offset based, at least in part, on the current direction signal, wherein the ZCD calibration offset is configured to adjust a timing of the zero-crossing detect signal in order to compensate for operational non-idealities associated with operation of the DC-DC converter.
5. The ZCD of claim 3 , wherein the generating the ZCD calibration offset comprises:
iteratively incrementing and/or decrementing the ZCD calibration offset based, at least in part, on a current direction of the output current in the output inductor determined approximately when a low-side switch of the power stage transitions to an off state;
determining a negative to positive transition of the current direction after incrementing the ZCD calibration offset; and
locking the ZCD calibration offset for a predetermined number of cycles of the power stage.
6. The ZCD of claim 1 , further comprising:
an idle release generator configured to:
receive the switch voltage and an input voltage for the power stage of the DC-DC converter; and
generate an idle release signal based, at least in part, on the received switch voltage and input voltage, wherein the idle release signal is configured to indicate the DC-DC converter is ready to exit an idle mode of the DC-DC converter.
7. The ZCD of claim 6 , wherein the idle release generator comprises:
a first comparator configured receive the switch voltage and generate a first comparator output indicating the switch voltage is greater than an idle mode threshold voltage preselected to be between ground and the output voltage;
a second comparator coupled to the first comparator output and configured to generate a second comparator output indicating the switch voltage is less than the input voltage, after the first comparator generates the first comparator output; and
a logic device configured to generate the idle release signal based, at least in part, on the first and second comparator outputs.
8. The ZCD of claim 1 , wherein the DC-DC converter comprises a discontinuous conduction mode (DCM) DC-DC converter, and wherein the power stage of the DCM DC-DC converter comprises:
a high-side field effect transistor (FET) coupled between an input voltage of the DC-DC converter and an input side of the output inductor; and
a low-side FET coupled between the input side of the output inductor and a ground for the DC-DC converter;
wherein the switch voltage is measured at the input side of the output inductor, and wherein the high-side FET and the low-side FET are controlled by respective high-side and low-side control signals provided by a controller of the DC-DC converter.
9. A DC-DC converter comprising the ZCD of claim 1 , wherein the DC-DC converter comprises:
a DC-DC converter controller configured to receive the output voltage of the power stage of the DC-DC converter and generate switch control signals to control a switching frequency of the power stage; and
an output load sensor configured to determine an output load status of the DC-DC converter, determine a peak current target value for the DC-DC converter based, at least in part, on the determined output load status, and provide the output load status and/or the peak current target value to the DC-DC converter controller, wherein the DC-DC converter controller is configured to:
selectively enable the ZCD based, at least in part, on the output voltage and/or the output load status of the DC-DC converter provided by the output load sensor; and
generate the switch control signals to adjust the switching frequency of the power stage based, at least in part, on the peak current target value provided by the output load sensor and/or the zero-crossing detect signal generated by the ZCD integrator.
10. A method of operating a zero-crossing detector (ZCD) for a direct current to direct current (DC-DC) converter, the method comprising:
receiving, by a ZCD integrator of the ZCD, a switch voltage and an output voltage of a power stage of the DC-DC converter;
generating, by the ZCD integrator, an integrator output based on the switch voltage and the output voltage of the power stage; and
generating, by an output comparator, a zero-crossing detect signal based, at least in part, on the integrator output and the output voltage of the power stage, wherein the zero-crossing detect signal indicates whether an output current in an output inductor of the power stage of the DC-DC converter is approximately zero.
11. The method of claim 10 , wherein the ZCD integrator comprises:
an integrator reset switch configured to reset the ZCD integrator during an idle mode of the DC-DC converter; and
a ZCD offset calibration applicator configured to receive the output voltage and a ZCD calibration offset and provide a corresponding calibrated output voltage to the output comparator, wherein the calibrated output voltage is configured to compensate for operational non-idealities associated with operation of the DC-DC converter.
12. The method of claim 10 , further comprising:
receiving, by a ZCD offset calibrator of the ZCD, the switch voltage; and
generating a ZCD calibration offset based, at least in part, on the received switch voltage, wherein the generating the zero-crossing detect signal is based, at least in part, on the ZCD calibration offset.
13. The method of claim 12 , wherein the ZCD offset calibrator comprises:
a current direction detector configured to receive the switch voltage, compare the switch voltage to a reference voltage for the DC-DC converter approximately when a low-side switch of the power stage transitions to an off state, and generate a current direction signal based, at least in part, on the comparison of the switch voltage and the reference voltage; and
a logic device configured to receive the current direction signal and generate the ZCD calibration offset based, at least in part, on the current direction signal, wherein the ZCD calibration offset is configured to adjust a timing of the zero-crossing detect signal in order to compensate for operational non-idealities associated with operation of the DC-DC converter.
14. The method of claim 12 , wherein the generating the ZCD calibration offset comprises:
iteratively incrementing and/or decrementing the ZCD calibration offset based, at least in part, on a current direction of the output current in the output inductor determined approximately when a low-side switch of the power stage transitions to an off state;
determining a negative to positive transition of the current direction after incrementing the ZCD calibration offset; and
locking the ZCD calibration offset for a predetermined number of cycles of the power stage.
15. The method of claim 10 , further comprising:
receiving, by an idle release generator, the switch voltage and an input voltage for the power stage of the DC-DC converter; and
generating an idle release signal based, at least in part, on the received switch voltage and input voltage, wherein the idle release signal is configured to indicate the DC-DC converter is ready to exit an idle mode of the DC-DC converter.
16. The method of claim 15 , wherein the idle release generator comprises:
a first comparator configured receive the switch voltage and generate a first comparator output indicating the switch voltage is greater than an idle mode threshold voltage preselected to be between ground and the output voltage;
a second comparator coupled to the first comparator output and configured to generate a second comparator output indicating the switch voltage is less than the input voltage, after the first comparator generates the first comparator output; and
a logic device configured to generate the idle release signal based, at least in part, on the first and second comparator outputs.
17. The method of claim 10 , wherein the DC-DC converter comprises a discontinuous conduction mode (DCM) DC-DC converter, and wherein the power stage of the DCM DC-DC converter comprises:
a high-side field effect transistor (FET) coupled between an input voltage of the DC-DC converter and an input side of the output inductor; and
a low-side FET coupled between the input side of the output inductor and a ground for the DC-DC converter;
wherein the switch voltage is measured at the input side of the output inductor, and wherein the high-side FET and the low-side FET are controlled by respective high-side and low-side control signals provided by a controller of the DC-DC converter.
18. The method of claim 10 , further comprising A DC-DC converter comprising the ZCD of claim 1 , wherein the DC-DC converter comprises:
selectively enabling the ZCD based, at least in part, on the output voltage and/or an output load status of the DC-DC converter provided by an output load sensor configured to determine the output load status of the DC-DC converter, determine a peak current target value for the DC-DC converter based, at least in part, on the determined output load status, and provide the output load status and/or the peak current target value to a DC-DC converter controller for the DC-DC converter; and
generating, by the DC-DC converter controller, switch control signals to adjust a switching frequency of the power stage of the DC-DC converter based, at least in part, on the peak current target value provided by the output load sensor and/or the zero-crossing detect signal generated by the ZCD integrator.