IP Library Granted Patent US 11,656,996
Granted Patent B2
US 11,656,996 · App. 17/186,542 · Granted May 23, 2023

Controller for managing order information of data, operation method thereof, and memory system including the same

Inventor: Eu Joon Byun (Gyeonggi-do, KR)
Assignee: SK hynix Inc.
G06F12/0882G06F3/0604G06F3/0647G06F3/0679G06F12/0238
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Quick Facts
Patent No.
US 11,656,996
App. No.
17/186,542
Granted
May 23, 2023
Kind
B2
Abstract

A memory system includes a memory device comprising a plurality of pages, and a controller suitable for storing data, inputted in response to a write command received from a host, in corresponding pages among the plurality of pages, wherein the controller generates and manages a bitmap table indicating order information of the inputted data according to the type of the write command.

Claims (51)

1. A memory system comprising:

a memory device comprising a plurality of pages; and

a controller suitable for storing data, inputted in response to a write command received from a host, in corresponding pages among the plurality of pages,

wherein the controller generates and manages a bitmap table indicating order information of the inputted data according to the type of the write command,

wherein the order information for a first type of the write command indicates that the inputted data are in a fixed order with respect to previous write data and corresponding write data, and the order information for a second type of the write command indicates that the inputted data are in a fixed order with respect to the corresponding write data,

wherein the controller, during a background operation, detects a target page among the plurality of pages and checks the logic level of a bit corresponding to the detected target page in the bitmap table,

wherein the controller, during the background operation, detects, as other target pages, pages adjacent to the detected target page in a first direction for the first type of the write command and pages adjacent to the detected target page in a second direction for the second type of the write command, based on the check result until the bit corresponding to a first target page is or changes to a second logic level, and

wherein the controller, during the background operation, migrates data of the detected target page and the detected other target pages to other pages among the plurality of pages.

2. The memory system of claim 1 , wherein the controller sets bits, corresponding to the corresponding pages in the bitmap table, to the same logic level in response to the first type of the write command indicating that the inputted data are in the fixed order with respect to the previous data and the corresponding write data.

3. The memory system of claim 2 , wherein the controller sets a first bit and the other bits of the bits, corresponding to the corresponding pages in the bitmap table, to different logic levels in response to the second type of the write command indicating that the inputted data are in the fixed order with respect to the corresponding write data.

4. The memory system of claim 3 , wherein the logic levels of set bits for the first type of write command is different than the logic levels of set bits for the second type of write command.

5. A controller comprising:

an address map management component suitable for managing an address map table indicating relationships between logical addresses of write data and physical addresses of pages in which the write data are stored, among a plurality of pages;

a bitmap management component suitable for setting bits indicating order information of the write data based on a type of a write command, and managing a bitmap table indicating the relationships between the set bits of the write data and the pages in which the write data are stored; and

a background control component suitable for performing a background operation on the plurality of pages based on the bitmap table,

wherein the bitmap management component sets bits of the bitmap table, corresponding to the pages in which the write data are stored, to a first logic level in response to a first type of the write command indicating that the write data are in a fixed order with respect to a previous data and corresponding write data, and for a second type of the write command indicates that the inputted data are in a fixed order with respect to the corresponding write data,

wherein the background control component detects a target page among the plurality of pages, and checks the logic level of a bit corresponding to the detected target page in the bitmap table, and detects, as other target pages, pages adjacent to the detected target page in a first direction for the first type of the write command and pages adjacent to the detected target page in a second direction for the second type of the write command, based on the check result until the bit corresponding to a first target page is or changes to a second logic level, and

wherein the background control component migrates data of the detected target page and the detected other target pages to other pages among the plurality of pages.

6. The controller of claim 5 , wherein, while setting the bits of the bitmap table, corresponding to the pages in which the write data are stored, to the first logic level, the bitmap management component sets a first bit of the bits to a second logic level different from the first logic level, in response to a second type of the write command indicating that the write data are in a fixed order without regard to the previous data.

7. The controller of claim 5 , wherein, when the bit corresponding to the detected target page has a first logic level, the background control component detects, as a first target page, a page adjacent to the detected target page in a first direction, for the first type write command, and checks the logic level of a bit corresponding to the first target page in the bitmap table.

8. The controller of claim 7 , wherein, until the bit corresponding to the first target page is a second logic level, the background control component continues to detect, as the first target page, pages adjacent to the first target page in the first direction.

9. The controller of claim 5 , wherein, regardless of the logic level of the bit corresponding to the detected target page, the background control component checks the logic level of a bit, corresponding to a page adjacent to the detected target page in a second direction for the second type write command, in the bitmap table.

10. The controller of claim 9 , wherein, when the bit corresponding to the page adjacent in the second direction has the first logic level, the background control component detects, as a second target page, the page adjacent in the second direction.

11. The controller of claim 10 , wherein, until the bit corresponding to the page adjacent in the second direction is the second logic level, the background control component continues to detect, as the second target page, pages adjacent to the detected target page in the second direction.

12. An operation method of a controller, comprising:

detecting a target page among a plurality of pages;

checking a logic level of a bit corresponding to the detected target page in a bitmap table; and

detecting, as the target page, a page adjacent to the detected target page, based on the check result,

wherein the bitmap table indicates order information of inputted data according to a type of a write command,

wherein the order information for a first type of the write command indicates that the inputted data are in a fixed order with respect to previous write data and corresponding write data, and the order information for a second type of the write command indicates that the inputted data are in a fixed order with respect to the corresponding write data, and

wherein the detecting of the page adjacent to the detected target page as the target page comprises:

where the bit corresponding to the detected target page is a first logic level,

detecting, as a first target page, a page adjacent to the detected target page in a first direction;

checking the logic level of a bit corresponding to the first target page in the bitmap table;

continuing to detect, as the first target page, pages adjacent to the first target page in the first direction, until the bit corresponding to the first target page is a second logic level; and

migrating data of the detected target page and the detected first target pages to other pages among the plurality of pages.

13. The operation method of claim 12 , wherein the detecting of the page adjacent to the detected target page as the target page comprises:

checking the logic level of a bit, corresponding to a page adjacent to the detected target page in a second direction, in the bitmap table;

detecting, for a second type write command, the page adjacent in the second direction as a second target page, when the bit corresponding to the page adjacent in the second direction is the first logic level; and

continuing to detect, as the second target page, pages adjacent to the detected target page in the second direction, until the bit corresponding to the page adjacent in the second direction is the second logic level.

14. A memory system comprising:

a memory device including a plurality of pages; and

a memory controller suitable for:

receiving multiple pieces of write data associated with a write command from a host;

storing the multiple pieces of the write data in corresponding pages among the plurality of pages;

generating a bitmap table based on the type of the write command, the bitmap table including multiple bits respectively corresponding to the multiple pieces or write data, each bit indicating whether or not the corresponding piece of write data is to be processed after a previous piece of write data is processed;

selecting a target page for a background operation among the corresponding pages, and one or more pages adjacent to the target page, using the bitmap table, bits of the bitmap tables of the target and adjacent pages having the same respective values; and

performing the background operation on the target and adjacent pages,

wherein the multiple bits of the bitmap table are set to a first logic level in response to a first type of the write command indicating that the corresponding piece of write data are in a fixed order with respect to a previous piece of write data,

wherein the memory controller detects the target page among the plurality of pages, checks the logic level of a bit corresponding to the detected target page in the bitmap table, and detects, as other target pages, pages adjacent to the detected target page, based on the check result until the bit corresponding to a first target page is or changes to a second logic level, and

wherein the memory controller migrates data of the detected target page and the detected other target pages to other pages among the plurality of pages.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 7, 2024
From: SK HYNIX INC.
To: MIMIRIP LLC
Reel/Frame 067335/0246 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 26, 2021
From: BYUN, EU JOON
To: SK HYNIX INC.
Reel/Frame 055425/0033 →
Priority Claims (1)
KR 10-2020-0125764 · Sep 28, 2020 · national
Continuity (1)
Related Publication 20220100671A1 · Mar 31, 2022