IP Library Granted Patent US 11,599,436
Granted Patent B2
US 11,599,436 · App. 17/189,810 · Granted Mar 7, 2023

Systems and methods for repairing corruption to BIOS boot critical memory variables

Inventors: Craig L. Chaiken (Pflugerville, TX); Siva Subramaniam Rajan (Austin, TX)
Assignee: Dell Products L.P.
G06F11/2284G06F9/4401G06F11/079G06F11/0793G06F11/1417G06F13/36G06F2201/805
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,599,436
App. No.
17/189,810
Granted
Mar 7, 2023
Kind
B2
Abstract

An information handling system may include a processor and a basic input/output system (BIOS) comprising a program of instructions executable on the processor, the basic input/output system configured to, upon occurrence of a predetermined number of failures to complete a power-on/self-test (POST) of the information handling system: for each particular critical boot variable of the BIOS stored in a memory associated with the BIOS, read a backup variable for the particular critical boot variable, if available, and write a value of the backup variable as the critical boot variable; and attempt to reboot the information handling system with values of the backup variables used for the critical boot variables.

Claims (35)

1. An information handling system comprising:

a processor; and

a basic input/output system (BIOS) comprising a program of instructions executable on the processor, the basic input/output system configured to:

during production of the information handling system, determine which variables associated with the BIOS are critical boot variables and flag such variables as critical boot variables; and

upon occurrence of a predetermined number of failures to complete a power-on/self-test (POST) of the information handling system:

for each particular critical boot variable of the BIOS stored in a memory associated with the BIOS, read a backup variable for the particular critical boot variable, if available, and write a value of the backup variable as the critical boot variable; and

attempt to reboot the information handling system with values of the backup variables used for the critical boot variables.

2. The information handling system of claim 1 , wherein the BIOS is further configured to:

upon failure to complete POST following the reboot, for each particular critical boot variable of the BIOS, read a default value for the particular critical boot variable and write the default value as the critical boot variable; and

attempt to again reboot the information handling system with values of the default variables used for the critical boot variables.

3. The information handling system of claim 1 , wherein the memory is a non-volatile random access memory associated with the memory.

4. The information handling system of claim 1 , wherein the BIOS is further configured to, in response to performing a write operation associated with a critical boot variable, write a backup variable to the memory in addition to writing a new value of the critical boot variable to the memory.

5. A method comprising, in an information handling system comprising a processor and a basic input/output system (BIOS) comprising a program of instructions executable on the processor:

during production of the information handling system, determining which variables associated with the BIOS are critical boot variables and flagging such variables as critical boot variables; and

upon occurrence of a predetermined number of failures to complete a power-on/self-test (POST) of the information handling system:

for each particular critical boot variable of the BIOS stored in a memory associated with the BIOS, reading a backup variable for the particular critical boot variable, if available, and writing a value of the backup variable as the critical boot variable; and

attempting to reboot the information handling system with values of the backup variables used for the critical boot variables.

6. The method of claim 5 , further comprising:

upon failure to complete POST following the reboot, for each particular critical boot variable of the BIOS, reading a default value for the particular critical boot variable and writing the default value as the critical boot variable; and

attempting to again reboot the information handling system with values of the default variables used for the critical boot variables.

7. The method of claim 5 , wherein the memory is a non-volatile random access memory associated with the memory.

8. The method of claim 5 , further comprising, in response to performing a write operation associated with a critical boot variable, writing a backup variable to the memory in addition to writing a new value of the critical boot variable to the memory.

9. An article of manufacture comprising:

a processor;

a non-transitory computer-readable medium; and

computer-executable instructions carried on the computer-readable medium, the instructions readable by a processor, the instructions, when read and executed, for causing the processor to, in a basic input/output system (BIOS) of an information handling system:

during production of the information handling system, determine which variables associated with the BIOS are critical boot variables and flag such variables as critical boot variables; and

upon occurrence of a predetermined number of failures to complete a power-on/self-test (POST) of the information handling system:

for each particular critical boot variable of the BIOS stored in a memory associated with the BIOS, read a backup variable for the particular critical boot variable, if available, and write a value of the backup variable as the critical boot variable; and

attempt to reboot the information handling system with values of the backup variables used for the critical boot variables.

10. The article of claim 9 , the instructions for further causing the processor to:

upon failure to complete POST following the reboot, for each particular critical boot variable of the BIOS, read a default value for the particular critical boot variable and write the default value as the critical boot variable; and

attempt to again reboot the information handling system with values of the default variables used for the critical boot variables.

11. The article of claim 9 , wherein the memory is a non-volatile random access memory associated with the memory.

12. The article of claim 9 , the instructions for further causing the processor to, in response to performing a write operation associated with a critical boot variable, write a backup variable to the memory in addition to writing a new value of the critical boot variable to the memory.

Assignments (10)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (056295/0280) Recorded Jun 10, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 062022/0255 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (056295/0124) Recorded Jun 10, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 062022/0012 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (056295/0001) Recorded Jun 10, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 062021/0844 →
RELEASE OF SECURITY INTEREST Recorded Nov 2, 2021
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 058297/0332 →
SECURITY INTEREST Recorded May 19, 2021
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 056295/0124 →
SECURITY INTEREST Recorded May 19, 2021
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 056295/0001 →
SECURITY INTEREST Recorded May 19, 2021
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 056295/0280 →
CORRECTIVE ASSIGNMENT TO CORRECT THE MISSING PATENTS THAT WERE ON THE ORIGINAL SCHEDULED SUBMITTED BUT NOT ENTERED PREVIOUSLY RECORDED AT REEL: 056250 FRAME: 0541. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 17, 2021
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
Reel/Frame 056311/0781 →
SECURITY AGREEMENT Recorded May 14, 2021
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
Reel/Frame 056250/0541 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 2, 2021
From: CHAIKEN, CRAIG L.; RAJAN, SIVA SUBRAMANIAM
To: DELL PRODUCTS L.P.
Reel/Frame 055459/0837 →
Continuity (1)
Related Publication 20220283918A1 · Sep 8, 2022
Cited By (1)
US 12,579,019