Compact protection device for protecting an integrated circuit against electrostatic discharge

1. An integrated circuit, comprising:

a power supply terminal;

a reference terminal;

a first signal terminal;

a second signal terminal;

a first protection device coupled between the first signal terminal and the power supply terminal;

a second protection device coupled between the first signal terminal and the reference terminal;

a third protection device coupled between the second signal terminal and the power supply terminal;

a fourth protection device coupled between the second signal terminal and the reference terminal; and

a MOS protection transistor having a first electrode coupled to said signal terminal and a second electrode coupled to said second signal terminal, wherein a gate of the MOS protection transistor is indirectly coupled to the reference terminal, and a substrate of the MOS protection transistor is coupled to the reference terminal via a first common resistor.

2. The integrated circuit according to claim 1 , wherein the gate of the MOS protection transistor is coupled to the reference terminal via a first trigger circuit.

3. The integrated circuit according to claim 2 , wherein the first trigger circuit includes the first common resistor.

4. The integrated circuit of claim 1 , wherein the gate of the MOS protection transistor is coupled to the reference terminal via said first common resistor.

5. The integrated circuit of claim 1 :

wherein the first protection device comprises a first MOS transistor having a first electrode coupled to the first signal terminal and a second electrode coupled to the power supply terminal,

wherein the second protection device comprises a second MOS transistor having a first electrode coupled to said first signal terminal and a second electrode coupled to the reference terminal,

wherein gates of the first and second MOS transistors, substrates of the first and second MOS transistors and the substrate of the MOS protection transistor are connected to a first terminal of the first common resistor, and wherein a second terminal of the first common resistor is connected to the reference terminal.

6. The integrated circuit according to claim 5 , wherein the first and second MOS transistors and the MOS protection transistor are implemented in one and the same substrate and have mutually connected gates.

7. The integrated circuit according to claim 5 , wherein the first and second MOS transistors are implemented in one and the same substrate and have mutually connected gates.

8. The integrated circuit according to claim 5 , further comprising a third MOS transistor having a first electrode coupled to the power supply terminal, a second electrode coupled to the reference terminal, a gate indirectly connected to the reference terminal and a substrate connected to the first terminal of the first common resistor.

9. The integrated circuit according to claim 8 , wherein the first, second and third MOS transistors are implemented in one and the same substrate and have mutually connected gates.

10. The integrated circuit according to claim 8 , wherein the gate of the third MOS transistor is coupled to the reference terminal via said first common resistor.

11. The integrated circuit according to claim 5 , wherein the gates of the first and second MOS transistors and the MOS protection transistor are coupled to the reference terminal via a first trigger circuit.

12. The integrated circuit according to claim 11 , wherein the first trigger circuit includes the first common resistor.

13. The integrated circuit of claim 1 :

wherein the third protection device comprises a fourth MOS transistor having a first electrode coupled to the second signal terminal and a second electrode coupled to the power supply terminal,

wherein the fourth protection device comprises a fifth MOS transistor having a first electrode coupled to said second signal terminal and a second electrode coupled to the reference terminal,

wherein gates of the fourth and fifth MOS transistors and substrates of the fourth and fifth MOS transistors are connected to a first terminal of the second common resistor, and wherein a second terminal of the second common resistor is connected to the reference terminal.

14. The integrated circuit according to claim 13 , wherein the fourth and fifth MOS transistors are implemented in one and the same substrate and have mutually connected gates.

15. The integrated circuit according to claim 13 , further comprising a sixth MOS transistor having a first electrode coupled to the power supply terminal, a second electrode coupled to the reference terminal, a gate indirectly connected to the reference terminal and a substrate connected to the first terminal of the second common resistor.

16. The integrated circuit according to claim 15 , wherein the fourth, fifth and sixth MOS transistors are implemented in one and the same substrate and have mutually connected gates.

17. The integrated circuit according to claim 15 , wherein the gate of the sixth MOS transistor is coupled to the reference terminal via said second common resistor.

18. The integrated circuit according to claim 13 , wherein the gates of the fourth and fifth MOS transistors are coupled to the reference terminal via a second trigger circuit.

19. The integrated circuit according to claim 18 , wherein the second trigger circuit includes the second common resistor.

20. The integrated circuit according to claim 1 , further comprising an electronic module that electrically interconnects the first and second signal terminals.