Semiconductor device
According to one embodiment, a semiconductor device includes a substrate, first stacked components, second stacked components, and a coating resin. The first stacked components include first chips and are stacked on a surface of the substrate. The second stacked components include second chips and are stacked on the surface. The coating resin covers the surface, the first stacked components, and the second stacked components. A first top surface of a second farthest one of the first chips away from the surface differs in position in a first direction from a second top surface of second farthest one of the second chips away from the surface.
1. A semiconductor device comprising:
a substrate including a surface facing in a first direction and a plurality of electrodes on the surface;
a plurality of first stacked components including a plurality of first chips, the plurality of first stacked components being stacked on the surface;
a plurality of first wires that connects the plurality of first chips and the plurality of electrodes;
a plurality of second stacked components including a plurality of second chips, the plurality of second stacked components being stacked on the surface;
a plurality of second wires that connects the plurality of second chips and the plurality of electrodes; and
a coating resin that covers the surface, the plurality of first stacked components, the plurality of first wires, the plurality of second stacked components, and the plurality of second wires, the coating resin including an outer surface that faces in the first direction and is provided with a recess that forms a mark, wherein
the plurality of first stacked components including the plurality of first chips each includes a first top surface facing in the first direction,
the plurality of second stacked components including the plurality of second chips each includes a second top surface facing in the first direction,
the first top surface of a second farthest one of the plurality of first chips away from the surface differs in position in the first direction from the second top surface of a second farthest one of the plurality of second chips away from the surface, and
the recess is located on the outer surface outside a region lying over either of the first top surface and the second top surface in the first direction, whichever is farther from the surface, the first top surface being of a farthest one of the plurality of first stacked components away from the surface, and the second top surface being of a farthest one of the plurality of second stacked components away from the surface.
2. The semiconductor device according to claim 1 , wherein the number of the plurality of first stacked components is different from the number of the plurality of second stacked components.
3. The semiconductor device according to claim 1 , wherein the number of the plurality of first stacked components is equal to the number of the plurality of second stacked components.
4. The semiconductor device according to claim 1 , wherein the thickness of one of the plurality of first chips is different from the thickness of one of the plurality of second chips.
5. The semiconductor device according to claim 1 , wherein
the plurality of first chips includes a plurality of first memory chips that stores information, and
the plurality of second chips includes a plurality of second memory chips that stores information, and a controller chip that controls the plurality of first memory chips and the plurality of second memory chips.
6. The semiconductor device according to claim 5 , further comprising:
a plurality of third wires that connects the controller chip and the plurality of electrodes; and
a bonding layer that bonds one of the plurality of second stacked components and the controller chip together, wherein
the controller chip is mounted on the surface, and
at least part of the third wire is embedded in the bonding layer.
7. The semiconductor device according to claim 1 , further comprising:
a controller chip on the surface;
a plurality of third wires that connects the controller chip and the plurality of electrodes; and
a bonding layer that bonds one of the plurality of second stacked components and the surface together, wherein
the plurality of first chips includes a plurality of first memory chips that stores information and is controlled by the controller chip,
the plurality of second chips includes a plurality of second memory chips that stores information and is controlled by the controller chip, and
at least part of the third wire is embedded in the bonding layer.
8. The semiconductor device according to claim 1 , wherein the plurality of second stacked components includes a spacer between the plurality of second chips, or between one of the plurality of second chips and the surface.
9. The semiconductor device according to claim 8 , wherein
one of the plurality of second chips includes a terminal connected to one of the plurality of second wires, and is supported by the spacer, and
the terminal is placed over the spacer in the first direction.
10. The semiconductor device according to claim 8 , wherein
the spacer comprises an inorganic material, and
at least one of the plurality of first chips and the plurality of second chips includes a layer comprising a material including the inorganic material.
11. The semiconductor device according to claim 8 , wherein
the coating resin comprises a synthetic resin, and
the spacer comprises the synthetic resin.
12. The semiconductor device according to claim 1 , wherein a farthest one of the plurality of first stacked components away from the surface is overlapped with a farthest one of the plurality of second stacked components away from the surface in a plane view as seen from the first direction.