Deep reactive ion etching process for fluid ejection heads
View Patent ↗An ejection head chip and method for a fluid ejection device and a method for reducing a silicon shelf width between a fluid supply via and a fluid ejector stack. The ejection head chip includes a silicon substrate and a fluid ejector stack deposited on the silicon substrate, wherein at least one metal layer of the fluid ejector stack is isolated from a fluid supply via etched in the ejection head chip by an encapsulating material.
1. An ejection head chip for a fluid ejection device comprising, a silicon substrate and a fluid ejector stack deposited on the silicon substrate, wherein at least one metal layer of the fluid ejector stack is isolated from a fluid supply via etched in the ejection head chip by an encapsulating material, wherein the encapsulating material comprises silicon oxide or silicon dioxide derived from a chemical vapor deposition of an organic silicon compound.
2. The ejection head chip of claim 1 , wherein a silicon shelf width between the fluid supply via and the fluid ejector stack ranges from about 0 to about 20 microns.
3. The ejection head chip of claim 1 , wherein the at least one metal layer comprises tantalum.
4. The ejection head chip of claim 1 , wherein the fluid supply via is etched in the silicon substrate from a fluid ejector stack side of the substrate using a deep reactive ion etch (DRIE) process.
5. The ejection head chip of claim 1 , wherein the fluid supply via has a minimum width ranging from about 60 to about 520 microns.
6. The ejection head chip of claim 1 , wherein the encapsulating material further comprises an inter-metal dielectric layer.
7. The ejection head chip of claim 6 , wherein the inter-metal dielectric layer comprises a doped or undoped diamond-like-carbon material.
8. The ejection head chip of claim 1 , wherein the encapsulating material further comprises a silicon nitride layer.
9. The ejection head chip of claim 1 , wherein the at least one metal layer is isolated from an edge of the fluid supply via by from about 1.5 to about 2.5 microns of encapsulating material.
10. A method for reducing a silicon shelf width between a fluid supply via and a fluid ejector stack comprising,
depositing at least one insulating layer on a silicon substrate,
depositing a silicon nitride layer on the at least one insulating layer,
depositing a metal layer on the silicon nitride layer,
encapsulating the metal layer in an encapsulating material, wherein the encapsulating material boarders two sides of the fluid supply via,
applying an etch mask to the fluid ejector stack to define a location for the fluid supply via, and
etching the fluid supply via in the silicon substrate with a minimum width ranging from about 60 to about 520 microns, to provide a silicon shelf having a width ranging from about 0 to about 20 microns.
11. The method of claim 10 , wherein the metal layer comprises tantalum.
12. The method of claim 10 , wherein the fluid supply via is etched in the silicon substrate from a fluid ejector stack side of the substrate using a deep reactive ion etch (DRIE) process.
13. The method of claim 10 , wherein the encapsulating material comprises silicon oxide or silicon dioxide derived from a chemical vapor deposition of an organic silicon compound as a protective overcoat layer.
14. The method of claim 13 , wherein the encapsulating material further comprises an inter-metal dielectric layer.
15. The method of claim 14 , wherein the inter-metal dielectric layer comprises a doped or undoped diamond-like-carbon material.
16. The method of claim 13 , wherein the encapsulating material further comprises a silicon nitride layer.
17. The method of claim 10 , wherein the at least one metal layer is isolated from an edge of the fluid supply via by from about 1.5 to about 2.5 microns of encapsulating material.