Thermal sensor circuit

1. A temperature sensing circuit, comprising:

a thermistor comprising a first MOS transistor having a first drain, a first source, a first gate, a first body and a first back gate, wherein the first MOS transistor is configured to operate in weak inversion mode with a negative temperature coefficient drain-source resistance;

an output terminal coupled to the first source and configured to generate a positive temperature coefficient output voltage; and

a current source comprising a second MOS transistor having a second drain, a second source, a second gate, a second body and a second back gate, wherein the second gate is coupled to the first source and configured to impose a drain-source current of the first MOS transistor; and

wherein the first body and second body are floating, and

wherein the first back gate and the second back gate are directly electrically connected to a ground node.

2. The temperature sensing circuit of claim 1 , wherein the first and second MOS transistors are supported by a semiconductor on insulator (SOI) substrate, said SOI substrate including semiconductor film layer over a buried oxide layer over a semiconductor substrate, and wherein the semiconductor film layer provides the first and second bodies and wherein the first and second back gates are provided within the semiconductor substrate.

3. The temperature sensing circuit of claim 2 , wherein the SOI substrate is a fully depleted SOI substrate.

4. The temperature sensing circuit of claim 1 , wherein the first drain is directly electrically connected to a supply voltage node.

5. The temperature sensing circuit of claim 1 , wherein the second source and second drain are directly electrically connected to the ground node.

6. The temperature sensing circuit of claim 1 , wherein the second source is directly electrically connected to the ground node and the second drain is configured to receive a bias voltage.

7. The temperature sensing circuit of claim 1 , wherein the first gate is directly electrically connected to the first drain.

8. The temperature sensing circuit of claim 1 , wherein the first gate of the first MOS transistor has a first gate oxide thickness, and wherein the second gate of the second MOS transistor has a second gate oxide thickness, and wherein the first gate oxide thickness is thicker than the second gate oxide thickness.

9. The temperature sensing circuit of claim 8 , wherein the first and second MOS transistors are supported by a semiconductor on insulator (SOI) substrate, said SOI substrate including semiconductor film layer over a buried oxide layer over a semiconductor substrate, and wherein the semiconductor film layer provides the first and second bodies and wherein the first and second back gates are provided within the semiconductor substrate.

10. The temperature sensing circuit of claim 9 , wherein the SOI substrate is a fully depleted SOI substrate.

11. The temperature sensing circuit of claim 8 , wherein the first drain is directly electrically connected to a supply voltage node.

12. The temperature sensing circuit of claim 8 , wherein the second source and second drain are directly electrically connected to the ground node.

13. The temperature sensing circuit of claim 8 , wherein the second source is directly electrically connected to the ground node and the second drain is configured to receive a bias voltage.

14. The temperature sensing circuit of claim 8 , wherein the first gate is directly electrically connected to the first drain.

15. The temperature sensing circuit of claim 1 , wherein the thermistor further comprises:

a third MOS transistor having a third drain which is coupled to the first source, a third source coupled to the output terminal, a third gate, a third body and a third back gate, wherein the third MOS transistor is configured to operate in weak inversion mode with a negative temperature coefficient drain-source resistance; and

wherein the third body is floating, and

wherein the third back gate is directly electrically connected to the ground node.

16. The temperature sensing circuit of claim 15 , wherein the first, second and third MOS transistors are supported by a semiconductor on insulator (SOI) substrate, said SOI substrate including semiconductor film layer over a buried oxide layer over a semiconductor substrate, and wherein the semiconductor film layer provides the first, second and third second bodies and wherein the first, second and third back gates are provided within the semiconductor substrate.

17. The temperature sensing circuit of claim 16 , wherein the SOI substrate is a fully depleted SOI substrate.

18. The temperature sensing circuit of claim 15 , wherein the first drain is directly electrically connected to a supply voltage node.

19. The temperature sensing circuit of claim 15 , wherein the second source and second drain are directly electrically connected to the ground node.

20. The temperature sensing circuit of claim 15 , wherein the second source is directly electrically connected to the ground node and the second drain is configured to receive a bias voltage.

21. The temperature sensing circuit of claim 15 , wherein the first gate is directly electrically connected to the first drain and wherein the third gate is directly electrically connected to the third drain.

22. The temperature sensing circuit of claim 15 , wherein the first gate of the first MOS transistor has a first gate oxide thickness, wherein the second gate of the second MOS transistor has a second gate oxide thickness, wherein the third gate of the third MOS transistor has a third gate oxide thickness, and wherein the first and third gate oxide thicknesses are thicker than the second gate oxide thickness.