Light emitting diode devices with defined hard mask opening

1. A light emitting diode (LED) device comprising:

a plurality of mesas defining pixels, each of the mesas comprising semiconductor layers, the semiconductor layers including an N-type layer, an active region, and a P-type layer, each of the mesas having a height less than or equal to their width;

a metal in a space between each of the mesas, the metal providing optical isolation between each of the mesas, and electrically contacting the N-type layer of each of the mesas along sidewalls of the N-type layers;

a dielectric material which insulates sidewalls of the P-type layer and the active region from the metal;

a current spreading layer on the P-type layer, the current spreading layer having a first portion and a second portion;

a P-contact layer on the first portion of the current spreading layer;

a dielectric layer on the second portion of the current spreading layer;

a guard layer covering the P-contact layer;

a hard mask layer on a first section of the guard layer above the second portion of the current spreading layer, the hard mask layer having an opening therein partially filled with a liner layer and partially filled with a P-metal material plug, a combination of the liner layer and the P-metal material plug having a width; and

a passivation film on the hard mask layer, the passivation film having a passivation film opening therein defining a width, the width of the passivation film opening being less than the width of the combination of the P-metal material plug and the liner layer, the passivation film covering a surface of the liner layer and a portion of the P-metal material plug.

2. A method of manufacturing a light emitting diode (LED) device comprising:

depositing a plurality of semiconductor layers including an N-type layer, an active region, and a P-type layer on a substrate;

depositing a hard mask layer over the P-type layer;

etching a portion of the semiconductor layers and the hard mask layer to form trenches and plurality of mesas defining pixels, each of the mesas comprising the semiconductor layers and each of the mesas having a height less than or equal to their width;

depositing a dielectric material in the trenches;

forming an opening in the hard mask layer, and etching the semiconductor layers to expose a surface of the substrate and a sidewall of the N-type layer;

depositing a liner layer on the substrate, including on surfaces of the opening in the hard mask layer, the dielectric material, the N-type layer, and substrate;

depositing an electrode metal on the liner layer;

planarizing the substrate to form an N-contact material electrically contacting the N-type layer of each of the mesas along sidewalls of the N-type layers, and a P-metal material plug on the liner layer in the opening of the hard mask layer, a combination of the P-metal material plug and the liner layer in the opening of the hard mask layer having a width; and

forming a passivation layer on the substrate and forming openings in the passivation layer defining a width, the width of each opening in the passivation layer being less than the width of the combination of the P-metal material plug and the liner layer, wherein the method further comprising, prior to depositing the hard mask layer over the P-type layer: depositing a current spreading layer on the P-type layer, the current spreading layer having a first portion and a second portion;

depositing a dielectric layer on the current spreading layer; forming a via in the dielectric layer defined by sidewalls of the dielectric layer and the first portion of the current spreading layer such that the dielectric layer is only on the second portion of the current spreading layer; depositing a P-contact layer on the substrate such that the P-contact layer is on a surface of the dielectric layer, sidewalls of the dielectric layer, and the first portion of the current spreading layer; depositing a guard layer covering the P-contact layer, wherein the hard mask layer and the liner layer in the opening of the hard mask layer are in direct contact with the P-contact layer.

3. The method of claim 2 , wherein the P-metal material plug comprises copper.

4. The method of claim 2 , wherein the width of the combination of the P-metal material plug and the liner layer is in a range of from 2 μm to 30 μm.

5. The method of claim 2 , wherein a pixel pitch of the plurality of mesas is in a range of from 5 μm to 100 μm.

6. The method of claim 2 , wherein the semiconductor layers have a thickness in a range of from 2 μm to 10 μm.