System and method of interfacing co-processors and input/output devices via a main memory system
A system for interfacing with a co-processor or input/output device is disclosed. According to one embodiment, the system includes a computer processing unit, a memory module, a memory bus that connects the computer processing unit and the memory module and a co-processing unit or input/output device, wherein the memory bus also connects the co-processing unit or input/output device to the computer processing unit.
1. An integrated circuit comprising:
a host interface circuit to receive commands from a host system coupled to the integrated circuit;
data scrambling circuitry configured to scramble and descramble data sent to and from the host system;
error correction code (ECC) circuitry configured to generate and check ECC bits for data sent to and received from the host system;
data interleaving circuitry configured to generate interleaved data or de-interleaved data;
swizzling circuitry configured to move data around within any bit position;
one or more configuration registers to store configuration information that identifies one of a plurality of configurations of the integrated circuit, wherein, in each of the plurality of configurations, a different combination of the data scrambling circuitry, the ECC circuitry, the data interleaving circuitry, or the swizzling circuitry is enabled; and
control circuitry to receive a first command from the host system and program the configuration information, stored in the one or more configuration registers, to enable a first combination of the data scrambling circuitry, the ECC circuitry, the data interleaving circuitry, or the swizzling circuitry, in response to the first command.
2. The integrated circuit of claim 1 , further comprising:
a memory interface circuit to couple to a solid state drive (SSD) controller; and
a control interface circuit to control one or more data buffer devices coupled to the integrated circuit.
3. The integrated circuit of claim 1 , further comprising:
a solid state drive (SSD) controller to control one or more non-volatile memory (NVM) devices coupled to the integrated circuit, wherein the SSD controller is to manage flow of data going to and from the NVM devices; and
a control interface circuit to control one or more data buffer devices coupled to the integrated circuit.
4. The integrated circuit of claim 1 , wherein the control circuitry is to read additional configuration information from a non-volatile memory device coupled to the integrated circuit or a microcontroller coupled to the integrated circuit and store the additional configuration information in the one or more configuration registers, wherein the additional configuration information comprises at least one of manufacturing calibration data, configuration override data, or memory module configuration data including a number of ranks of memory devices.
5. The integrated circuit of claim 1 , wherein the host interface circuit comprising:
registers; and
a phased-locked loop circuit, wherein the registers and phased-locked loop circuit reduce an electrical load on control lines between the integrated circuit and a memory controller of the host system.
6. The integrated circuit of claim 1 , wherein the control circuitry, prior to receiving the first command, is to:
receive a second command from the host system to initialize the integrated circuit;
receive a third command from the host system to train a data path between the host system and a plurality of memory devices coupled to the integrated circuit; and
receive a fourth command from the host system to perform a memory test on the plurality of memory devices.
7. The integrated circuit of claim 1 , wherein the control circuitry, after the configuration information is programmed, is to receive a fifth command from the host system to access one or more memory devices during a normal operation mode.
8. The integrated circuit of claim 1 , further comprising:
a command buffer to store a second command received from the host system;
a buffer check logic to determine whether the second command is complete; and
a memory interface logic to provide the second command from the command buffer to at least one of one or more memory devices in response to the second command being complete.
9. The integrated circuit of claim 1 , wherein the control circuitry comprises:
a command processor configured to generate direct memory access (DMA) descriptors of a second command received from the host system; and
a buffer check logic configured to determine whether the second command is complete.
10. The integrated circuit of claim 9 , wherein the buffer check logic is configured to read one or more bits from each portion of a plurality of portions of the second command and to determine that the one or more bits read from each portion together match a predetermined pattern.
11. A memory module comprising:
one or more memory devices; and
a device coupled to the one or more memory devices, the device comprising:
a host interface circuit to receive commands from a host system coupled to the device;
data scrambling circuitry configured to scramble and descramble data sent to and from the host system;
error correction code (ECC) circuitry configured to generate and check ECC bits for data sent to and received from the host system;
data interleaving circuitry configured to generate interleaved data or de-interleaved data;
swizzling circuitry configured to move data around within any bit position;
one or more configuration registers to store configuration information that identifies one of a plurality of configurations of the memory module, wherein, in each of the plurality of configurations, a different combination of the data scrambling circuitry, the ECC circuitry, the data interleaving circuitry, or the swizzling circuitry is enabled; and
control circuitry to receive a first command from the host system and program the configuration information, stored in the one or more configuration registers, to enable a first combination of the data scrambling circuitry, the ECC circuitry, the data interleaving circuitry, or the swizzling circuitry, in response to the first command.
12. The memory module of claim 11 , further comprising:
one or more memory devices;
a memory interface circuit to couple to a solid state drive (SSD) controller; and
a control interface circuit to control one or more data buffer devices coupled to the device.
13. The memory module of claim 11 , further comprising:
a solid state drive (SSD) controller to control one or more non-volatile memory (NVM) devices coupled to the device, wherein the SSD controller is to manage flow of data going to and from the NVM devices; and
a control interface circuit to control one or more data buffer devices coupled to the device.
14. The memory module of claim 11 , further comprising:
a command buffer to store a second command received from the host system;
a buffer check logic to determine whether the second command is complete; and
a memory interface logic to provide the second command from the command buffer to at least one of one or more memory devices in response to the second command being complete.
15. The memory module of claim 11 , further comprising:
a command processor configured to generate direct memory access (DMA) descriptors of a second command received from the host system; and
a buffer check logic configured to determine whether the second command is complete.
16. The CPIO module of claim 11 , further comprising:
a solid state drive (SSD) controller to control one or more non-volatile memory (NVM) devices coupled to the control logic, wherein the SSD controller is to manage flow of data going to and from the NVM devices; and
a control interface circuit to control one or more data buffer devices coupled to the control logic.
17. The CPIO module of claim 11 , further comprising:
a command buffer to store a second command received from the host system;
a buffer check logic to determine whether the second command is complete; and
a memory interface logic to provide the second command from the command buffer to at least one of one or more memory devices in response to the second command being complete.
18. The CPIO module of claim 11 , further comprising:
a command processor configured to generate direct memory access (DMA) descriptors of a second command received from the host system; and
a buffer check logic configured to determine whether the second command is complete.
19. A co-processing or input/output (CPIO) module comprising:
one or more CPIO devices; and
control logic coupled to the one or more CPIO devices, the control logic comprising:
a host interface circuit to receive commands from a host system coupled to the CPIO module;
data scrambling circuitry configured to scramble and descramble data sent to and from the host system;
error correction code (ECC) circuitry configured to generate and check ECC bits for data sent to and received from the host system;
data interleaving circuitry configured to generate interleaved data or de-interleaved data;
swizzling circuitry configured to move data around within any bit position;
one or more configuration registers to store configuration information that identifies one of a plurality of configurations of the CPIO module, wherein, in each of the plurality of configurations, a different combination of the data scrambling circuitry, the ECC circuitry, the data interleaving circuitry, or the swizzling circuitry is enabled; and
control circuitry to receive a first command from the host system and program the configuration information, stored in the one or more configuration registers, to enable a first combination of the data scrambling circuitry, the ECC circuitry, the data interleaving circuitry, or the swizzling circuitry, in response to the first command.
20. The CPIO module of claim 19 , further comprising:
one or more memory devices; and
a memory interface circuit to couple to a solid state drive (SSD) controller; and
a control interface circuit to control one or more data buffer devices coupled to the control logic.