System and method for the creation and provision of execution virtual context information
A system and method for virtual processor customization based upon the particular workload placed upon the virtual processor by one or more execution contexts within a given program or process. The customization serves to optimize the virtual processor architecture based upon a determination as to the size and/or type or virtual execution registers optimally suited for supporting a given execution context. This results in a time-variant processor architecture comprised of a virtual processor base and a virtual execution context.
1. A system including a processor and memory for generating context execution information comprising:
the processor configured to:
generate a constructor adapted to configure at least one virtual processor base and at least one virtual execution context in the memory, wherein the constructor is further adapted to:
generate at least one boot-strap instruction;
provide the at least one virtual processor base with the at least one generated boot-strap instruction, wherein the at least one virtual processor base is defined by parameters comprising at least one of a specification of an initial static register configuration and a specification of an initial dynamic register configuration;
initiate the execution of the at least one virtual execution context in response to the reception of the at least one generated boot-strap instruction by the at least one virtual processor base; and
retrieve and execute instructions from the at least one virtual execution context.
2. The system of claim 1 wherein the at least one boot-strap instruction comprises a memory address at which code required to initiate a process comprising the at least one virtual execution context.
3. The system of claim 1 wherein the instructions retrieved from the at least one virtual execution context comprise information for the optimization of the at least one virtual processor base and the at least one virtual execution context for the execution of a particular code.
4. The system of claim 1 wherein the constructor and the at least one virtual processor base are supported by a common system.
5. The system of claim 1 wherein the constructor and the at least one virtual processor base are each supported by separate systems.
6. The system of claim 1 wherein the at least one virtual processor base and the at least one virtual execution context are both supported within a single physical addressable memory device.
7. The system of claim 1 wherein the at least one virtual execution context is supported by an addressable memory linked to the at least one virtual processor base by a bus.
8. The system of claim 1 wherein at least one of the at least one virtual processor base and at least one virtual execution context comprises at least one of the following:
static random-access memory;
dynamic random-access memory; and
non-volatile memory.
9. A method for generating context execution information, in a system comprising a constructor adapted to configure at least one virtual processor base and at least one virtual execution context, the method comprising the steps of:
generating at least one boot-strap instruction;
providing the at least one virtual processor base with the at least one generated boot-strap instruction, wherein the at least one virtual processor base is defined by parameters comprising at least one of a specification of an initial static register configuration and a specification of an initial dynamic register configuration;
initiating the execution of the at least one virtual execution context in response to then the reception of the at least one generated boot-strap instruction by the at least one virtual processor base; and
retrieving and execute instructions from the at least one virtual execution context.
10. The method of claim 9 wherein the at least one boot-strap instruction comprises a memory address at which code required to initiate a process comprising the at least one virtual execution context.
11. The method of claim 9 wherein the instructions retrieved from the at least one virtual execution context comprise information for the optimization of the at least one virtual processor base and the at least one virtual execution context for the execution of a particular code.
12. The method of claim 9 wherein the constructor and the at least one virtual processor base are supported by a common system.
13. The method of claim 9 wherein the constructor and the at least one virtual processor base are each supported by separate systems.
14. The method of claim 9 wherein the at least one virtual processor base and the at least one virtual execution context are both supported within a single physical addressable memory device.
15. The method of claim 9 wherein the at least one virtual execution context is supported by an addressable memory linked to the at least one virtual processor base by a bus.
16. The method of claim 9 wherein at least one of the at least one virtual processor base and at least one virtual execution context comprises at least one of the following:
static random-access memory;
dynamic random-access memory; and
non-volatile memory.
17. One or more non-transitory computer-readable storage media having computer-executable instructions embodied thereon that, when executed by a computing system having a processor and memory causes the processor to:
generate context execution information in the memory comprising:
a constructor adapted to configure at least one virtual processor base and at least one virtual execution context, wherein the constructor is further adapted to:
generate at least one boot-strap instruction;
provide the at least one virtual processor base with the at least one generated boot-strap instruction, wherein the at least one virtual processor base is defined by parameters comprising at least one of a specification of an initial static register configuration and a specification of an initial dynamic register configuration;
initiate the execution of the at least one virtual execution context in response to the reception of the at least one generated boot-strap instruction by the at least one virtual processor base; and
retrieve and execute instructions from the at least one virtual execution context.
18. The media of claim 17 wherein the at least one boot-strap instruction comprises a memory address at which code required to initiate a process comprising the at least one virtual execution context.
19. The media of claim 17 wherein the instructions retrieved from the at least one virtual execution context comprise information for the optimization of the at least one virtual processor base and the at least one virtual execution context for the execution of a particular code.
20. The media of claim 17 wherein the constructor and the at least one virtual processor base are supported by a common system.
21. The media of claim 17 wherein the constructor and the at least one virtual processor base are each supported by separate systems.
22. The media of claim 17 wherein the at least one virtual processor base and the at least one virtual execution context are both supported within a single physical addressable memory device.
23. The media of claim 17 wherein the at least one virtual execution context is supported by an addressable memory linked to the at least one virtual processor base by a bus.
24. The media of claim 17 wherein at least one of the least one virtual processor base and at least one virtual execution context comprises at least one of the following:
static random-access memory;
dynamic random-access memory; and
non-volatile memory.