Apparatus and method for correcting an error in data transmission of a data processing system

1. A data processing system comprising:

a host including a first error correction code circuitry and configured to generate a write request, a logical address, and a first encoded data item encoded based on a hamming code, wherein the first encoded data item is associated with the write request and the logical address; and

a memory system coupled to the host via a communication line and a write buffer, the memory system comprising a controller having a second error correction code circuitry and configured to receive the first encoded data item transmitted along with the write request and the logical address from the host via the communication line,

wherein the controller is further configured to:

store the first encoded data item in the write buffer;

with the second error correction code circuitry, decode the first encoded data item stored in the write buffer based on the hamming code to detect and correct a first error in the first encoded data item to obtain a first error-corrected data item;

encode the first error-corrected data item based on an error correction code to generate a second encoded data item; and

transmit the second encoded data item to program the second encoded data item in a non-volatile memory device which is indicated by a physical address translated from the logical address.

2. The data processing system according to claim 1 , wherein the first error includes:

an error occurring in a data communication between the host and the controller; and

an error occurring while the first encoded data item is temporarily stored in the write buffer.

3. The data processing system according to claim 1 , wherein the controller is further configured to:

receive a read request from the host;

read the second encoded data item programmed in the non-volatile memory device;

decode the second encoded data item based on the error correction code to detect and correct a second error in the second encoded data item to obtain a second error-corrected data item;

encode the second error-corrected data item based on the hamming code to generate a first encoded read data item;

store the first encoded read data item in a read buffer; and

transmit the first encoded read data item, as a response for the read request, to the host.

4. The data processing system according to claim 3 , wherein the second error includes an error occurring in the non-volatile memory device.

5. The data processing system according to claim 1 , wherein the error correction code includes the hamming code.

6. The data processing system according to claim 1 , wherein the error correction code includes the hamming code and a checksum.

7. A memory system comprising:

a memory device including non-volatile memory cells; and

a controller, including a volatile memory device, configured to control the memory device, wherein the controller is further configured to:

receive a data packet including a write request, a logical address, a data item and a first error correction parity corresponding to the data item, the data packet transmitted from a host including a first error correction code circuitry and coupled to the memory system via a communication line and a write buffer, the first error correction parity generated based on a hamming code generated by the first error correction code circuitry of the host;

store the data packet in the volatile memory device; and

with a second error correction code circuitry in the controller, decode the data packet based on the first error correction parity to detect and correct a first error in the data packet, occurring in the data transmission channel, and a second error in the data packet occurring in the volatile memory device.

8. The memory system according to claim 7 , wherein:

the controller performs a data communication with the host via the data transmission channel according to a preset protocol; and

the first error includes a bit flip occurring in the data packet while the data packet is transmitted and received via the data transmission channel.

9. The memory system according to claim 7 , wherein the second error includes a bit flip generated by an operation or a structure of the volatile memory device.

10. The memory system according to claim 7 , wherein the first error correction parity is generated by an encoding process based on the hamming code.

11. The memory system according to claim 7 , wherein the controller is further configured to:

encode an error-corrected data item of which the first and second errors are corrected based on an error correction code to generate a second error correction parity; and

transmit an encoded data item including the second error correction parity to the memory device.

12. The memory system according to claim 11 , wherein the error correction code includes the hamming code.

13. The memory system according to claim 11 , wherein the controller is further configured to:

read the encoded data item in response to a read request input from the host; and

decode the encoded data item based on the error correction code to detect and correct a third error in the encoded data item.

14. The memory system according to claim 13 , wherein the third error includes an operation or a structure of the memory device.

15. The memory system according to claim 13 , wherein the controller is further configured to:

encode an error-corrected data item to generate the first error correction parity, the error-corrected data item being obtained after decoding the encoded data item in response to the read request; and

transmit the error-corrected data item along with the first error correction parity to the host.

16. The memory system according to claim 7 , wherein the controller is further configured to:

decode the data packet including the first error correction parity, input from the host, to detect and correct the first error in the data packet;

encode a first error-corrected data item, in which the first error is corrected based on a first error correction code, to generate a second encoded data item;

store the second encoded data item in a data buffer of the volatile memory device; and

decode the second encoded data item to detect and correct a second error in the second encoded data item.

17. The memory system according to claim 16 , wherein the controller is further configured to encode a second error-corrected data item based on a second error correction code to transmit an encoded data item to the memory device.

18. The memory system according to claim 7 , wherein the controller is further configured to:

decode the data packet including the first error correction parity, input from the host, to detect and correct the first error in the data packet;

encode a first error-corrected data item in which the first error is corrected based on a first error correction code to generate the second encoded data item including the data item and a parity item; and

transmit the data item and the parity item to the memory device separately; and

wherein the memory device is configured to decode the data item and the parity item based on the first error correction code to detect and correct the second error in the second encoded data, and to store the data item in the non-volatile memory cells.

19. The memory system according to claim 18 , wherein the memory device includes:

a data buffer configured to store the data item; and

a parity buffer configured to store a parity item generated based on the first error correction code.

20. A method for operating a memory system, the method comprising:

receiving a data packet including a write request, a logical address, a data item and a first error correction parity corresponding to the data item, the data packet transmitted from a host including a first error correction code circuitry and coupled to the memory system via a communication line and a write buffer, the first error correction parity generated based on a hamming code by the first error correction code circuitry of the host;

storing the data packet in a volatile memory device; and

with a second error correction code circuitry in a controller, decoding the data packet based on the first error correction parity to detect and correct a first error occurring in the data transmission channel and a second error occurring in the volatile memory device.