IP Library Granted Patent US 11,582,864
Granted Patent B2
US 11,582,864 · App. 17/197,878 · Granted Feb 14, 2023

Impedance matching within a signal transmission channel

Inventors: Sandor Farkas (Round Rock, TX); Bhyrav Mutnury (Austin, TX)
Assignee: Dell Products L.P.
H05K1/025H05K2201/09281H05K2201/09727
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Quick Facts
Patent No.
US 11,582,864
App. No.
17/197,878
Granted
Feb 14, 2023
Kind
B2
Abstract

A printed circuit board for an information handling system includes a trace, a routing component, and one or more intermediate components. The trace has a first impedance, and the routing component has a second impedance. The intermediate components have respective intermediate impedances. Each of the intermediate impedances has a corresponding value in a range between a value of the first impedance and a value of the second impedance. The one or more intermediate impedances reduce an impedance discontinuity between the trace and the routing component.

Claims (39)

1. A printed circuit board for an information handling system, the printed circuit board comprising:

a trace having a first impedance;

a routing component having a second impedance; and

one or more intermediate components having a respective intermediate impedance, each of the intermediate impedances have a corresponding value in a range between a value of the first impedance and a value of the second impedance, the intermediate impedances to reduce an impedance discontinuity between the trace and the routing component, wherein the one or more intermediate components include:

a first intermediate component having a first intermediate impedance, the first intermediate component in physical communication with the routing component;

a second intermediate component having a second intermediate impedance, the second intermediate component in physical communication with the first intermediate component; and

a third intermediate component having a third intermediate impedance, the third intermediate component in physical communication with and located in between the trace and the second intermediate component.

2. The printed circuit board of claim 1 , wherein the one or more intermediate components is a single tapered component having a varying impedance.

3. The printed circuit board of claim 2 , wherein the varying impedance is highest near the trace and lowest near the routing component.

4. The printed circuit board of claim 2 , wherein the single tapered component is thinnest near the trace, widens toward the routing component, and is thickest near the routing component.

5. The printed circuit board of claim 1 , wherein the one or more intermediate impedances of the respective one or more intermediate components spread the impedance discontinuity between the trace and the routing component over a length equal to a number of wavelengths of a signal transmitted along the trace, the one or more intermediate components, and the routing component.

6. The printed circuit board of claim 1 , wherein the first intermediate impedance is a lowest impedance of the one or more impedances, the third intermediate impedance is a highest impedance of the one or more impedances, and the second intermediate impedance is an impedance in between the first and third impedances.

7. The printed circuit board of claim 1 , wherein the one or more intermediate impedances are formed based on respective lengths and widths of the respective one or more intermediate components.

8. A method comprising:

determining a first impedance of a trace for a printed circuit board of an information handling system;

determining a second impedance of a routing component for the printed circuit board;

based on the first and second impedances, determining a first intermediate impedance for a first intermediate component;

based on the first impedance and the first intermediate impedance, determining a second intermediate impedance for a second intermediate component;

based on the first impedance and the second intermediate impedance, determining a third intermediate impedance for a third intermediate component; and

routing the trace, the first, second, and third intermediate components, and the routing component on the printed circuit board.

9. The method of claim 8 , wherein determining the first, second, and third intermediate impedances further comprises calculating a plurality of intermediate impedances for a single tapered intermediate component, wherein the plurality of intermediate impedances includes the first, second, and third intermediate impedances.

10. The method of claim 9 , further comprising based on the intermediate impedances of the single tapered intermediate component, determining a plurality of different widths for the single tapered intermediate component.

11. The method of claim 10 , further comprising routing the single tapered intermediate component between the first trace and the routing component with a smallest width of the single tapered intermediate component in physical communication with the trace and a largest width of the single tapered intermediate component in physical communication with the routing component.

12. The method of claim 8 , further comprising:

based on the first intermediate impedance, determining a first width and a first length of the first intermediate component;

based on the second intermediate impedance, determining a second width and a second length of the second intermediate component; and

based on the third intermediate impedance, determining a third width and a third length of the third intermediate component.

13. The method of claim 12 , wherein the routing of the trace, the first, second, and third intermediate components, and the routing component on the printed circuit board of the information handling system further comprises:

routing the first intermediate component in physical communication with the routing component;

routing the second intermediate component in physical communication with the first intermediate component; and

routing the third intermediate component in physical communication with and in between the second intermediate component and the trace.

14. A printed circuit board for an information handling system, the printed circuit board comprising:

a trace having a first impedance;

a routing component having a second impedance, the trace runs through the routing component; and

a plurality of intermediate components, each of the intermediate components having an intermediate impedance with a corresponding value in a range between a value of the first impedance and a value of the second impedance, a first of the intermediate components to reduce a first impedance discontinuity between the trace and a first side of the routing component, and a second of the intermediate components to reduce a first impedance discontinuity between the trace and a first side of the routing component.

15. The printed circuit board of claim 14 , wherein the first intermediate component is a first tapered component having a varying impedance.

16. The printed circuit board of claim 15 , wherein the varying impedance is highest near the trace and lowest near the routing component.

17. The printed circuit board of claim 15 , wherein the first tapered component is thinnest near the trace, widens toward the routing component, and is thickest near the routing component.

18. The printed circuit board of claim 14 , wherein each of the intermediate impedances of the respective intermediate components spread the impedance discontinuity between the trace and the routing component over a length equal to a number of wavelengths of a signal transmitted along the trace, the one or more intermediate components, and the routing component.

Assignments (10)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (056295/0280) Recorded Jun 10, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 062022/0255 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (056295/0124) Recorded Jun 10, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 062022/0012 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (056295/0001) Recorded Jun 10, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 062021/0844 →
RELEASE OF SECURITY INTEREST Recorded Nov 2, 2021
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 058297/0332 →
SECURITY INTEREST Recorded May 19, 2021
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 056295/0124 →
SECURITY INTEREST Recorded May 19, 2021
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 056295/0001 →
SECURITY INTEREST Recorded May 19, 2021
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 056295/0280 →
CORRECTIVE ASSIGNMENT TO CORRECT THE MISSING PATENTS THAT WERE ON THE ORIGINAL SCHEDULED SUBMITTED BUT NOT ENTERED PREVIOUSLY RECORDED AT REEL: 056250 FRAME: 0541. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 17, 2021
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
Reel/Frame 056311/0781 →
SECURITY AGREEMENT Recorded May 14, 2021
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
Reel/Frame 056250/0541 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 11, 2021
From: FARKAS, SANDOR; MUTNURY, BHYRAV
To: DELL PRODUCTS, LP
Reel/Frame 055563/0069 →