Memory circuit and write method
View Patent ↗A memory circuit includes a memory array including a plurality of memory cells, each memory cell including a gate structure including a ferroelectric layer and a channel layer adjacent to the gate structure, the channel layer including a metal oxide material. A driver circuit is configured to output a gate voltage to the gate structure of a memory cell, the gate voltage having a positive polarity and a first magnitude in in a first write operation and a negative polarity and a second magnitude in in a second write operation, and to control the second magnitude to be greater than the first magnitude.
1. A memory circuit comprising:
a memory array comprising a plurality of memory cells, each memory cell of the plurality of memory cells comprising:
a gate structure comprising a conductive layer and a ferroelectric layer; and
a channel layer adjacent to the gate structure, wherein
the ferroelectric layer is positioned between the conductive layer and the channel layer, and
the channel layer comprises a metal oxide material; and
a driver circuit configured to output a gate voltage to the conductive layer of the gate structure of a memory cell of the plurality of memory cells,
wherein
the gate voltage has a positive polarity and a first magnitude in a first write operation,
the gate voltage has a negative polarity and a second magnitude in a second write operation, and
the driver circuit is configured to control the second magnitude to be greater than the first magnitude.
2. The memory circuit of claim 1 , wherein
the channel layer of each memory cell of the plurality of memory cells is positioned between a source contact and a drain contact of the memory cell, and
the memory circuit is configured to apply a ground voltage level to each of the source and drain contacts during each of the first and second write operations.
3. The memory circuit of claim 1 , wherein the metal oxide material of the channel layer of each memory cell of the plurality of memory cells comprises indium gallium zinc oxide (IGZO).
4. The memory circuit of claim 1 , wherein the first magnitude has a value ranging from 2 volts to 2.5 volts.
5. The memory circuit of claim 1 , wherein the second magnitude has a value ranging from 3.5 volts to 5 volts.
6. The memory circuit of claim 1 , wherein the first magnitude has a value of approximately one half a value of the second magnitude.
7. The memory circuit of claim 1 , wherein the gate structure of each memory cell of the plurality of memory cells comprises an n-type work function layer configured to adjust a work function by less than 0.5 electron-volts.
8. The memory circuit of claim 1 , wherein
the memory cell of the plurality of memory cells is configured to have a first threshold voltage level responsive to the first write operation and a second threshold voltage level responsive to the second write operation, and
the first threshold voltage level is less than the second threshold voltage level by at least 0.5 volts.
9. The memory circuit of claim 8 , further comprising a sense amplifier configured to determine a programmed state of the memory cell of the plurality of memory cells based on the first threshold voltage level being less than the second threshold voltage level by at least 0.5 volts.
10. A method of writing data to a memory cell, the method comprising:
performing a first write operation on the memory cell by applying a gate voltage to a conductive layer of a gate structure and a ground voltage level to a channel layer comprising a metal oxide material, the gate structure comprising a ferroelectric layer between the conductive layer and the channel layer, and the gate voltage having a positive polarity and a first magnitude; and
performing a second write operation on the memory cell by applying the gate voltage to the conductive layer and the ground voltage level to the channel layer, the gate voltage having a negative polarity and a second magnitude greater than the first magnitude.
11. The method of claim 10 , wherein the applying the ground voltage level to the channel layer comprises the metal oxide material comprising indium gallium zinc oxide (IGZO).
12. The method of claim 10 , wherein
the channel layer is positioned adjacent to the ferroelectric layer and between a source contact and a drain contact, and
the applying the ground voltage level to the channel layer in each of the first and second write operations comprises applying the ground voltage level to each of the source and drain contacts.
13. The method of claim 10 , wherein at least one of the performing the first write operation or the performing the second write operation comprises shifting a threshold voltage of the memory cell by greater than 0.5 volts.
14. The method of claim 13 , further comprising using a sense amplifier to perform a read operation based on the threshold voltage of the memory cell.
15. The method of claim 10 , wherein
the applying the gate voltage to the conductive layer in the first write operation comprises the positive polarity and the first magnitude having a gate voltage duration, and
the applying the gate voltage to the conductive layer in the second write operation comprises the negative polarity and the second magnitude having the gate voltage duration.
16. The method of claim 10 , wherein
the applying the gate voltage to the conductive layer in the first write operation comprises the first magnitude having a value ranging from 2 volts to 2.5 volts, and
the applying the gate voltage to the conductive layer in the second write operation comprises the second magnitude having a value ranging from 3.5 volts to 5 volts.
17. The method of claim 10 , wherein
the applying the gate voltage to the conductive layer in the first write operation comprises the first magnitude having a first value, and
the applying the gate voltage to the conductive layer in the second write operation comprises the second magnitude having a second value approximately equal to twice the first value.
18. A memory circuit comprising:
a control circuit;
a plurality of memory cells, each memory cell of the plurality of memory cells comprising:
a gate terminal coupled to a gate structure comprising a conductive layer and a layer; and
a source terminal and a drain terminal coupled to a channel layer adjacent to the gate structure, wherein
the layer is positioned between the conductive layer and the channel layer, and
the channel layer comprises indium gallium zinc oxide (IGZO);
a word line driver coupled to the gate terminals of the memory cells of the plurality of memory cells; and
a read/write (R/W) interface coupled to the source and drain terminals of the memory cells of the plurality of memory cells,
wherein the control circuit is configured to, for a selected memory cell of the plurality of memory cells
perform a first write operation by causing the R/W interface to ground each of the source and drain terminals, and the word line driver to output a gate voltage to the gate terminal having a positive polarity and a first magnitude, and
perform a second write operation by causing the R/W interface to ground each of the source and drain terminals, and the word line driver to output the gate voltage to the gate terminal having a negative polarity and a second magnitude greater than the first magnitude.
19. The memory circuit of claim 18 , wherein the control circuit is configured to control the first magnitude to be less than three volts and the second magnitude to be greater than three volts.
20. The memory circuit of claim 18 , wherein
the gate voltage is configured to cause the selected memory cell of the plurality of memory cells to have a first threshold voltage level responsive to the first write operation and a second threshold voltage level responsive to the second write operation, and
the first threshold voltage level is less than the second threshold voltage level by at least 0.5 volts.