On-board integrated enclosure for electromagnetic compatibility shielding
A printed circuit board (PCB) and a method of manufacturing the same is described. The PCB includes a substrate defining a major plane and an integrated electromagnetic interference and compatibility (EMC/EMI) shielding enclosure configured to enclose the substrate. The shielding enclosure includes a metallic top layer deposited on top of the major plane of the substrate so as to envelop an uppermost layer of the substrate, a metallic bottom layer deposited on bottom of the major plane of the substrate so as to envelop a bottommost layer of the substrate, and a metallic side layer formed along a length of one or more edges of the substrate to electrically connect the metallic top layer and the metallic bottom layer.
1. A printed circuit board comprising:
a substrate defining a major plane; and
an integrated electromagnetic interference and compatibility (EMC/EMI) shielding enclosure configured to enclose the substrate, the shielding enclosure including:
a metallic top layer deposited on top of the major plane of the substrate so as to envelope an uppermost layer of the substrate;
a metallic bottom layer deposited on bottom of the major plane of the substrate so as to envelop a bottommost layer of the substrate;
a metallic side layer formed along a length of one or more edges of the substrate to electrically connect the metallic top layer and the metallic bottom layer;
a first opening on a first side of one of the metallic top layer or the metallic bottom layer configured for mounting thereon one or more functional circuit elements; and
a second opening on a second side of one of the metallic top layer or the metallic bottom layer configured for mounting thereon of a connector, opposite the first side, for coupling to a shielded communications cable.
2. The printed circuit board of claim 1 , wherein the metallic side layer of the EMC/EMI shielding enclosure is formed of a copper plating electrically connecting the metallic top layer and the metallic bottom layer to form a metallic enclosure disposed in propinquity to, and enveloping, the printed circuit board.
3. The printed circuit board of claim 1 , wherein the metallic side layer of the EMC/EMI shielding enclosure is formed by a plurality of stitching vias electrically connecting the metallic top layer and the metallic bottom layer.
4. The printed circuit board of claim 3 , wherein the metallic side layer of the EMC/EMI shielding enclosure is formed by two or more rows of the plurality of stitching vias.
5. The printed circuit board of claim 1 , wherein the substrate further comprises:
a first surface and a second surface;
a plurality of high-density interconnect vias penetrating the first surface and extending partially through the printed circuit board toward the second surface, the high-density interconnect vias configured to interconnect at least one component to the printed circuit board; and
a plurality of electrical connectors disposed in a region of the second surface opposite the high-density interconnect vias and configured to interface with one or more signal processing components disposed on the second surface.
6. The printed circuit board of claim 5 , wherein the plurality of high-density interconnect vias comprise one of: blind vias, buried vias, and micro-vias.
7. The printed circuit board of claim 1 , wherein the EMC/EMI shielding enclosure further comprises a third opening between the first opening and the second opening, configured for mounting thereon of a surface mounted capacitor configured to couple a digital grounding layer and a cable grounding layer.
8. The printed circuit board of claim 1 , wherein the substrate further comprises:
an embedded capacitor, formed on an internal layer of the printed circuit board, configured to couple a digital ground layer and a cable grounding layer, wherein the metallic top layer is deposited above the embedded capacitor.
9. The printed circuit board of claim 1 , wherein the metallic top layer and the metallic bottom layer form a continuous enclosure over the uppermost layer of the substrate and the bottommost layer of the substrate respectively.
10. A method of manufacturing a printed circuit board comprising an integrated electromagnetic compatibility/electromagnetic interference (EMC/EMI) shielding enclosure, the method comprising:
depositing a metallic top layer on top of a substrate so as to envelope an uppermost layer of the substrate;
depositing a metallic bottom layer on bottom of the substrate so as to envelop a bottommost layer of the substrate;
forming a metallic side layer along a length of one or more edges of the substrate to electrically connect the metallic top layer and the metallic bottom layer;
forming a first opening on a first side of one of the metallic top layer or the metallic bottom layer configured for mounting thereon of functional circuit elements; and
forming a second opening on a second side of one of the metallic top layer or the metallic bottom layer configured for mounting thereon of a connector, opposite the first side, for coupling to a shielded communications cable.
11. The method of claim 10 , wherein depositing the metallic side layer comprises:
electroplating copper material on an edge of the substrate electrically connecting the metallic top layer and the metallic bottom layer.
12. The method of claim 10 , wherein depositing the metallic side layer comprises:
stitching a plurality of vias along an edge of the substrate electrically connecting the metallic top layer and the metallic bottom layer.
13. The method of claim 12 , wherein the metallic side layer of the EMC/EMI shielding enclosure is formed by stitching two or more rows of the plurality of vias.
14. The method of claim 10 , further comprising:
forming a plurality of penetrating holes through a first surface and a second surface of the substrate; and
inserting a plurality of high-density interconnect vias penetrating the first surface and extending partially through the printed circuit board toward the second surface, wherein the high-density interconnect vias are configured to interconnect at least one component to the printed circuit board.
15. The method of claim 14 , wherein inserting the plurality of high-density interconnect vias comprises:
inserting of blind vias, buried vias, and micro-vias penetrating the first surface and extending partially through the printed circuit board toward the second surface.
16. The method of claim 10 , further comprising:
forming a third opening between the first opening and the second opening; and
mounting a surface-mounted capacitor configured to couple a digital ground and a cable ground at the third opening.
17. The method of claim 10 , further comprising:
forming an embedded capacitor on an internal layer of the printed circuit board, wherein the embedded capacitor is configured to couple a digital ground layer and a cable grounding layer; and
depositing the metallic top layer above the embedded capacitor.
18. The method of claim 10 , wherein depositing the metallic top layer and the metallic bottom layer further comprises:
depositing the metallic top layer and the metallic bottom layer to form a continuous enclosure over the uppermost layer of the substrate and the bottommost layer of the substrate respectively.