Systems and methods for thread management for modern workspaces
Systems and methods are provided for management of processor thread used in support of workspaces operating on an IHS (Information Handling System), where the workspaces operate in isolation from the operating system of the IHS. A remote workspace orchestration service manages deployment of workspaces on the IHS. The workspaces are instantiated and operate according to a workspace definition provided by the workspace orchestration service. A remote access controller of the IHS determine one or more processor threads of the IHS used in support of the workspaces. The remote access controller monitors memory utilization by the processor threads used in support of the workspaces in order to detect memory thrashing resulting from the operation of a particular workspace. Based on the monitored memory utilization, the processor threads used in support of the workspaces are modified in order to reduce memory thrashing during the operation of the workspaces.
1. A method for thread management for a plurality of workspaces operating on an Information Handling System (IHS), the method comprising:
registering thread management capabilities of the IHS with a workspace orchestration service that is remote from the IHS and that manages deployment of the plurality of workspaces on the IHS;
instantiating the plurality of workspaces, where each workspace operates according to a respective workspace definition that is provided by the workspace orchestration service;
determining one or more processor threads of the IHS used in support of each of the plurality of workspaces;
monitoring memory utilization by the one or more processor threads used in support of each of the plurality of workspaces; and
based on the monitored memory utilization by the one or more processor threads, modifying processor core assignments of processor threads used in support of one or more of the plurality of workspaces.
2. The method of claim 1 , wherein the method further comprises receiving, from the workspace orchestration service, a handle for thread management communications with a first workspace of the plurality of workspaces.
3. The method of claim 2 , wherein the handle comprises an API (Application Programming Interface) for use by the first workspace in reporting application events occurring within the first workspace.
4. The method of claim 3 , wherein the application events comprise notifications of specific software applications launched in the first workspace.
5. The method of claim 1 , wherein the IHS comprises a multi-core processor wherein respective processor cores of the multi-core processor are designated for use with specific cache memories of the IHS.
6. The method of claim 5 , wherein the monitored memory utilization comprises monitoring of instances of one or more threads operating on a first of the processor cores accessing a cache memory that is not designated for use by the first processor core.
7. The method of claim 1 , further comprising:
monitoring memory utilization by the modified processor thread assignments used in support of each of the plurality of workspaces; and
determining whether the modified processor thread assignments provide improved memory utilization.
8. The method of claim 1 , wherein the memory utilization by the one or more processor threads used in support of each of the plurality of workspaces is monitored by a remote access controller of the IHS.
9. The method of claim 8 , wherein the remote access controller interfaces with a memory controller of the IHS via an out-of-band coupling to monitor the memory utilization by the one or more processor threads.
10. An Information Handling System (IHS) supporting thread management for a plurality of workspaces operating on the IHS, the IHS comprising:
an embedded controller comprising a logic unit and a memory storing program instructions that, upon execution by the logic unit, cause the embedded controller to:
register thread management capabilities of the IHS with a workspace orchestration service that is remote from the IHS and that manages deployment of the plurality of workspaces on the IHS;
determine one or more processor threads operating on a multi-core processor in support of each of the plurality of workspaces; and
monitor memory utilization by the one or more processor threads used in support of each of the plurality of workspaces;
the multi-core processor comprising a two or more of processor cores, wherein respective processor cores are designated for use with specific cache memories of the IHS; and
a memory coupled to the multi-core processor, the memory storing program instructions that, upon execution by the multi-core processor, cause the multi-core processor to:
instantiate the plurality of workspaces, where each workspace operates according to a respective workspace definition that is provided by the workspace orchestration service; and
based on the monitored memory utilization by the one or more processor threads, modify processor core assignments of processor threads used in support of one or more of the plurality of workspaces.
11. The IHS of claim 10 , wherein the execution of the instructions further causes the multi-core processor to receive, from the workspace orchestration service, a handle for thread management communications with a first workspace of the plurality of workspaces.
12. The IHS of claim 11 , wherein the thread management communications comprise notifications of specific software applications being launched within the first workspace.
13. The IHS of claim 10 , wherein the monitored memory utilization comprises monitoring of instances of one or more threads operating on a first of the processor cores accessing a cache memory that is not designated for use by the first processor core.
14. The IHS of claim 10 , wherein the execution of the instructions further causes the multi-core processor to:
monitor memory utilization by the modified processor thread assignments used in support of each of the plurality of workspaces; and
determine whether the modified processor thread assignments provide improved memory utilization.
15. A system supporting thread management for a plurality of workspaces operating on an Information Handling System (IHS), the system comprising:
the IHS;
a server located remote from the IHS, the server providing a workspace orchestration service, the workspace orchestration service configured to manage deployment of workspaces on the IHS; and
the IHS comprising:
a multi-core processor comprising a plurality or processing cores;
an embedded controller configured to:
register thread management capabilities of the IHS with the workspace orchestration service;
determine one or more processor threads operating on the multi-core processor in support of each of the plurality of workspaces; and
monitor memory utilization by the one or more processor threads used in support of each of the plurality of workspaces; and
an IHS memory coupled to the multi-core processor, the IHS memory storing program instructions that, upon execution by the multi-core processor, cause the IHS to:
instantiate the plurality of workspaces, where each workspace operates according to a respective workspace definition that is provided by the workspace orchestration service; and
based on the monitored memory utilization by the one or more processor threads, modify processor core of processor threads used in support of one or more of the plurality of workspaces.
16. The system of claim 15 , wherein the execution of the instructions further causes the multi-core processor to receive, from the orchestration service, a handle for thread management communications with a first workspace of the plurality of workspaces.
17. The system of claim 16 , wherein the thread management communications comprise notifications of specific software applications launched in the first workspace.
18. The system of claim 15 , wherein the monitored memory utilization comprises monitoring of instances of one or more threads operating on a first of the processor cores accessing a cache memory that is not designated for use by the first processor core.
19. The system of claim 15 , wherein the execution of the instructions further causes the multi-core processor to:
monitor memory utilization by the modified processor thread assignments used in support of each of the plurality of workspaces; and
determine whether the modified processor thread assignments provide improved memory utilization.
20. The system of claim 15 , wherein respective processor cores of the multi-core processor are designated for use with specific cache memories of the IHS.