Micro-fabricated, stress-engineered members formed on passivation layer of integrated circuit
A release layer is formed on a surface of an integrated circuit wafer. The surface is passivated and includes metal contact materials. A stress-engineered film having an intrinsic stress profile is deposited over the release layer. The stress-engineered film is patterned and the release layer is undercut etched so that a released portion of the patterned stress-engineered film is released from the surface while leaving an anchor portion fixed to the surface. The intrinsic stress profile in the stress-engineered film biases the released portion away from the surface. The released portion is placed entirely within an area defined by the metal contact material.
1. A method comprising:
activating a surface of an integrated circuit wafer with an accelerated stream of atoms, the surface comprising passivation and metal contact materials;
while bombarding the surface with the stream of atoms, depositing a part of a release layer on the surface;
depositing a remainder of the release layer without the atom bombardment;
depositing a stress-engineered film having an intrinsic stress profile over the release layer;
patterning the stress-engineered film; and
undercut etching the release layer so that a released portion of the patterned stress-engineered film is released from the surface while leaving an anchor portion fixed to the surface, the intrinsic stress profile in the stress-engineered film biasing the released portion away from the surface, the released portion placed entirely within an area defined by the metal contact materials.
2. The method of claim 1 , where the anchor portion is entirely within the area defined by the metal contact materials.
3. The method of claim 1 further comprising removing the release layer using a selective etchant that does not substantially etch the passivation surface.
4. The method of claim 3 wherein the selective etchant comprises NH 4 OH and H 2 O 2 .
5. The method of claim 1 , wherein the metal contact materials comprise noble metal contacts.
6. The method of claim 5 , wherein the noble metal contacts comprise Au or alloys thereof.
7. The method of claim 1 wherein the stress-engineered film comprises an alloy of molybdenum and chrome.
8. The method of claim 1 , wherein at least a portion of the stream of atoms are ionized.
9. The method of claim 8 , wherein the stream of atoms comprises an Ar stream.
10. The method of claim 1 , wherein the release layer comprises one of Ti, an alloy of Ti, or, Si x O y N z , where x, y, and z are fractional constituents between 0 and 1.
11. The method of claim 1 , further comprising forming a layer of a second metal over the metal contact materials prior to depositing the release layer, the second metal resistant to the undercut etching.
12. The method of claim 1 , wherein the released portion comprises an arcuate spring.
13. The method of claim 12 , wherein the released portion extends out of plane by 2 μm to 600 μm.
14. A method comprising:
depositing a release layer on a surface of an integrated circuit wafer, the surface comprising passivation and metal contact materials, wherein the release layer comprises Ti or an alloy thereof;
depositing a stress-engineered film having an intrinsic stress profile over the release layer;
patterning the stress-engineered film;
undercut etching the release layer so that a released portion of the patterned stress-engineered film is released from the surface while leaving an anchor portion fixed to the surface, the intrinsic stress profile in the stress-engineered film biasing the released portion away from the surface, the released portion placed entirely within an area defined by the metal contact materials; and
after undercut etching the release layer, removing a second portion of the release layer using a chemical comprising NH 4 OH and H 2 O 2 .
15. A method comprising:
providing a self-contained integrated circuit that is formed via a first process; and
forming an elastic member on the integrated circuit via a second process comprising:
depositing a release layer on a passivation surface and metal contact of the integrated circuit;
forming the elastic member on the release layer, the elastic member having an intrinsic stress profile;
covering the release layer and the elastic member with a photoresist;
forming an opening in the photoresist over the elastic member, the opening entirely within an area defined by the metal contact;
undercut etching the release layer through the opening to form a free end while leaving an anchor portion fixed to the release layer, the intrinsic stress profile in the elastic member biasing the free end of the elastic member away from the integrated circuit to form an out of plane structure upon release of the free end; and
after undercut etching the release layer, removing the release layer using a selective etchant that does not substantially etch the passivation surface.
16. The method of claim 15 , further comprising interfacing the integrated circuit with an electrical device such that the free end of the elastic member deflects when contacting a contact of the electrical device and forms an electrical path therebetween.
17. The method of claim 15 , wherein depositing the release layer comprises:
activating the passivation surface with an accelerated stream of atoms;
while bombarding the passivation surface with the stream of atoms, depositing a part of the release layer on the passivation surface; and
depositing a remainder of the release layer without the atom bombardment.
18. The method of claim 17 , wherein at least a portion of the stream of atoms are ionized.
19. The method of claim 18 , wherein the stream of atoms comprises an Ar stream.
20. The method of claim 17 , wherein the release layer comprises one of Ti, an alloy of Ti, or, Si x O y N z , where x, y, and z are fractional constituents between 0 and 1.