IP Library Granted Patent US 11,249,891
Granted Patent B1
US 11,249,891 · App. 17/208,647 · Granted Feb 15, 2022

Machine-learning framework for testing feedback controller robustness

Inventors: Peter Patel-Schneider (Westfield, NJ); Ion Matei (Sunnyvale, CA); Alexandre Perez (San Mateo, CA); Ron Zvi Stern (Palo Alto, CA); Johan de Kleer (Los Altos, CA)
Assignee: Palo Alto Research Center Incorporated
G06F11/3688G06F8/44G06F8/53G06F11/3684G06F40/47G06N3/0427G06N3/08
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Quick Facts
Patent No.
US 11,249,891
App. No.
17/208,647
Granted
Feb 15, 2022
Kind
B1
Abstract

A method includes receiving a subject-matter expert (SME) interpretable model. The method further includes converting, by a processing device, the SME interpretable model into a functional mockup unit (FMU). The method further includes integrating the FMU into a control software project (CSP). The method further includes compiling the CSP into binary code.

Claims (49)

1. A method, comprising:

receiving a subject-matter expert (SME) interpretable model;

converting, by a processing device, the SME interpretable model into a functional mockup unit (FMU);

integrating the FMU into a control software project (CSP);

compiling the CSP into binary code;

testing a robustness of a feedback controller against reconstruction based on the binary code, wherein testing the robustness of the feedback controller against reconstruction comprises:

transforming the binary code into high-level code using a neural decompiler; and

processing a low-level abstract syntax tree (AST) corresponding to the high-level code using a natural language processing (NLP)-based transformer to produce a high-level AST.

2. The method of claim 1 , wherein the SME interpretable model is based on a Modelica language.

3. The method of claim 1 , wherein to convert the SME interpretable model into the FMU the method comprises using a functional mockup interface (FMI) standard.

4. The method of claim 1 , wherein the CSP is expressed in C++ source code.

5. The method of claim 1 , further comprising providing the binary code as training data to a machine learning model trained to reconstruct a firmware of the feedback controller.

6. The method of claim 1 , further comprising:

generating a test SME interpretable model from the high-level AST;

analyzing the test SME interpretable model for syntax errors; and

comparing the test SME interpretable model to the SME interpretable model to determine inconstancies.

7. A system comprising:

a memory to store binary code; and

a processing device, operatively coupled to the memory, to:

receive a subject-matter expert (SME) interpretable model;

covert the SME interpretable model into a functional mockup unit (FMU);

integrate the FMU into a control software project (CSP);

compile the CSP into the binary code;

transform the binary code into high-level code using a neural decompiler;

process a low-level abstract syntax tree (AST) corresponding to the high-level code using a natural language processing (NLP)-based transformer to produce a high-level AST; and

test a robustness of a feedback controller against reconstruction based on the binary code.

8. The system of claim 7 , wherein the SME interpretable model is based on a Modelica language.

9. The system of claim 7 , wherein to convert the SME interpretable model into the FMU the processing device is further to use a functional mockup interface (FMI) standard.

10. The system of claim 7 , wherein the CSP is expressed in C++ source code.

11. The system of claim 7 , the processing device further to provide the binary code as training data to a machine learning model trained to reconstruct a firmware of the feedback controller.

12. The system of claim 7 , wherein to test the robustness of the feedback controller against reconstruction, the processing device is further to:

generate a test SME interpretable model from the high-level AST;

analyze the test SME interpretable model for syntax errors; and

compare the test SME interpretable model to the SME interpretable model to determine inconstancies.

13. A non-transitory computer-readable storage medium having instructions stored thereon that, when executed by a processing device, cause the processing device to:

receive a subject-matter expert (SME) interpretable model;

covert, by the processing device, the SME interpretable model into a functional mockup unit (FMU);

integrate the FMU into a control software project (CSP);

compile the CSP into binary code;

transform the binary code into high-level code using a neural decompiler;

process a low-level abstract syntax tree (AST) corresponding to the high-level code using a natural language processing (NLP)-based transformer to produce a high-level AST; and

test a robustness of a feedback controller against reconstruction based on the binary code.

14. The non-transitory computer-readable storage medium of claim 13 , wherein the SME interpretable model is based on a Modelica language.

15. The non-transitory computer-readable storage medium of claim 13 , wherein the CSP is expressed in C++ source code.

16. The non-transitory computer-readable storage medium of claim 13 , the processing device further to provide the binary code as training data to a machine learning model trained to reconstruct a firmware of the feedback controller.

17. The non-transitory computer-readable storage medium of claim 13 , wherein to test the robustness of the feedback controller against reconstruction, the processing device is further to:

generate a test SME interpretable model from the high-level AST;

analyze the test SME interpretable model for syntax errors; and

compare the test SME interpretable model to the SME interpretable model to determine inconstancies.

Assignments (9)
SECOND LIEN NOTES PATENT SECURITY AGREEMENT Recorded Jul 2, 2025
From: XEROX CORPORATION
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 071785/0550 →
FIRST LIEN NOTES PATENT SECURITY AGREEMENT Recorded Apr 11, 2025
From: XEROX CORPORATION
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 070824/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT RF 064760/0389 Recorded Feb 13, 2024
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: XEROX CORPORATION
Reel/Frame 068261/0001 →
SECURITY INTEREST Recorded Feb 13, 2024
From: XEROX CORPORATION
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 066741/0001 →
SECURITY INTEREST Recorded Nov 20, 2023
From: XEROX CORPORATION
To: JEFFERIES FINANCE LLC, AS COLLATERAL AGENT
Reel/Frame 065628/0019 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVAL OF US PATENTS 9356603, 10026651, 10626048 AND INCLUSION OF US PATENT 7167871 PREVIOUSLY RECORDED ON REEL 064038 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jun 28, 2023
From: PALO ALTO RESEARCH CENTER INCORPORATED
To: XEROX CORPORATION
Reel/Frame 064161/0001 →
SECURITY INTEREST Recorded Jun 22, 2023
From: XEROX CORPORATION
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 064760/0389 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 20, 2023
From: PALO ALTO RESEARCH CENTER INCORPORATED
To: XEROX CORPORATION
Reel/Frame 064038/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 24, 2021
From: PATEL-SCHNEIDER, PETER; MATEI, ION; PEREZ, ALEXANDRE; STERN, RON ZVI; DE KLEER, JOHAN
To: PALO ALTO RESEARCH CENTER INCORPORATED
Reel/Frame 055702/0779 →
Cited By (1)
US 12,487,912