IP Library Granted Patent US 11,569,379
Granted Patent B2
US 11,569,379 · App. 17/209,200 · Granted Jan 31, 2023

Semiconductor device and semiconductor device manufacturing method

Inventor: Masahiro Hatakenaka (Tokyo, JP)
Assignee: ABLIC Inc.
H01L29/7833H01L21/2253H01L21/26513H01L29/66492
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Quick Facts
Patent No.
US 11,569,379
App. No.
17/209,200
Granted
Jan 31, 2023
Kind
B2
Abstract

In the semiconductor device, a high-concentration diffusion layer and a low-concentration diffusion layer are disposed around a drain diffusion layer of an ESD protection element. The high-concentration diffusion layer is separated from a gate electrode, and a medium concentration LDD diffusion layer is disposed in a separation gap. Variations in characteristics are suppressed by reducing thermal treatment on the high-concentration diffusion layer and a medium concentration diffusion layer.

Claims (42)

1. A semiconductor device comprising:

a semiconductor substrate;

a second conductivity-type low concentration diffusion layer provided on the semiconductor substrate;

a gate electrode provided on a surface of the second conductivity-type low concentration diffusion layer with an interposition of a gate oxide film;

a first conductivity-type source diffusion layer provided on a surface of the semiconductor substrate which is positioned on one side of the gate electrode, and a first conductivity-type drain diffusion layer provided on the surface of the semiconductor substrate which is positioned on the other side of the gate electrode to be separated from the gate electrode;

a first conductivity-type drain LDD diffusion layer provided on the surface of the semiconductor substrate between the drain diffusion layer and a portion directly under an end of the gate electrode on the drain diffusion layer side, wherein the first conductivity-type drain LDD diffusion layer is provided in contact with the portion directly under the end of the gate electrode on the drain diffusion layer side;

a first conductivity-type high concentration diffusion layer provided to include the drain diffusion layer from a position closer to the drain diffusion layer than an end of the drain LDD diffusion layer on the source diffusion layer side and having a concentration of impurities higher than that of the drain LDD diffusion layer and lower than that of the drain diffusion layer; and

a first conductivity-type low concentration diffusion layer provided to include the drain LDD diffusion layer, the high-concentration diffusion layer, and the drain diffusion layer from the surface of the semiconductor substrate below the gate electrode and having a concentration of impurities lower than that of the drain LDD diffusion layer.

2. The semiconductor device according to claim 1 , further comprising:

a second conductivity-type medium concentration region covering the source diffusion layer and extending to a channel below the gate electrode.

3. The semiconductor device according to claim 1 , further comprising:

a first conductivity-type source LDD diffusion layer provided on the surface of the semiconductor substrate between the source diffusion layer and a channel.

4. The semiconductor device according to claim 3 , further comprising:

a second conductivity-type medium concentration region covering the source diffusion layer and the source LDD diffusion layer and extending to a channel below the gate electrode.

5. A semiconductor device comprising:

a semiconductor substrate;

a second conductivity-type low concentration diffusion layer provided inwardly from a surface of the semiconductor substrate;

a first conductivity-type source diffusion layer and a first conductivity-type drain diffusion layer provided on a surface of the semiconductor substrate on an inner side of the second conductivity-type low concentration diffusion layer with an interval;

a field oxide film provided from a position between the source diffusion layer and the drain diffusion layer to an end of the drain diffusion layer;

a gate oxide film provided from an end of the field oxide film on the source side to an end of the source diffusion layer on a surface of the second conductivity-type low concentration diffusion layer;

a gate electrode provided to cover portions of the gate oxide film and the field oxide film;

a first conductivity-type drain LDD diffusion layer provided on the surface of the semiconductor substrate below the field oxide film, wherein the first conductivity-type drain LDD diffusion layer is provided in contact with a portion directly under an end of the gate electrode on the drain diffusion layer side;

a first conductivity-type high concentration diffusion layer provided to include the drain diffusion layer from a position closer to the drain diffusion layer than an end of the drain LDD diffusion layer on the source diffusion layer side and having a concentration of impurities higher than that of the drain LDD diffusion layer and lower than that of the drain diffusion layer; and

a first conductivity-type low concentration diffusion layer provided to include the drain LDD diffusion layer, the high-concentration diffusion layer, and the drain diffusion layer from the surface of the semiconductor substrate below the gate electrode and having a concentration of impurities lower than that of the drain LDD diffusion layer.

6. The semiconductor device according to claim 5 , further comprising:

a second conductivity-type medium concentration region covering the source diffusion layer and extending to a channel below the gate electrode.

7. The semiconductor device according to claim 5 , further comprising:

a first conductivity-type source LDD diffusion layer provided on the surface of the semiconductor substrate between the source diffusion layer and a channel.

8. The semiconductor device according to claim 7 , further comprising:

a second conductivity-type medium concentration region covering the source diffusion layer and the source LDD diffusion layer and extending to the channel below the gate electrode.

9. A semiconductor device manufacturing method comprising:

ion-implanting second conductivity-type impurities on a semiconductor substrate;

ion-implanting first conductivity-type impurities to form a low-concentration diffusion layer by thermal diffusion;

ion-implanting first conductivity-type impurities to form a high-concentration diffusion layer;

forming a gate oxide film;

forming a gate electrode;

ion-implanting first conductivity-type impurities to form a source diffusion layer and a drain diffusion layer; and

ion-implanting first conductivity-type impurities to form an LDD diffusion layer which is a medium concentration diffusion layer,

wherein the source diffusion layer is provided on a surface of the semiconductor substrate which is positioned on one side of the gate electrode, and the drain diffusion layer is provided on the surface of the semiconductor substrate which is positioned on the other side of the gate electrode to be separated from the gate electrode,

the LDD diffusion layer is provided on the surface of the semiconductor substrate between the drain diffusion layer and a portion directly under an end of the gate electrode on the drain diffusion layer side, wherein the drain LDD diffusion layer is provided in contact with the portion directly under the end of the gate electrode on the drain diffusion layer side,

the high-concentration diffusion layer is provided to include the drain diffusion layer from a position closer to the drain diffusion layer than an end of the drain LDD diffusion layer on the source diffusion layer side and has a concentration of impurities higher than that of the drain LDD diffusion layer and lower than that of the drain diffusion layer, and

the low-concentration diffusion layer is provided to include the drain LDD diffusion layer, the high-concentration diffusion layer, and the drain diffusion layer from the surface of the semiconductor substrate below the gate electrode and has a concentration of impurities lower than that of the drain LDD diffusion layer.

Assignments (3)
CHANGE OF ADDRESS Recorded Jun 8, 2023
From: ABLIC INC.
To: ABLIC INC.
Reel/Frame 064021/0575 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 14, 2023
From: POTTATHIL, RAVEENDRAN; DESHMUKH, SANJAY; KHARAT, KIRAN
To: ACCUDX CORPORATION
Reel/Frame 063088/0581 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 23, 2021
From: HATAKENAKA, MASAHIRO
To: ABLIC INC.
Reel/Frame 055677/0530 →