Memory system and operating method to set target command delay time to merge and process read commands

1. A memory system comprising:

a memory device; and

a memory controller for communicating with the memory device and controlling the memory device,

wherein the memory controller

executes a read operation by setting a command delay time, which is time used for determining whether to merge and process read commands, for each of a plurality of time periods, and

sets a target command delay time, from among the command delay times set for each of the plurality of time periods, to be used for determining whether to merge and process a subsequent read command with one or more prior read commands based on the execution result of the read operation for each of the plurality of time periods,

wherein data requested by read commands inputted during the command delay time is processed simultaneously when the read commands are merged and processed,

wherein read commands inputted during each of the plurality of time periods is merged and processed based on the command delay time set for the each of the plurality of time periods, and

wherein the execution result of the read operation for each of the plurality of time periods includes the number of read commands input during the corresponding time period, the number of read requests input to the memory device during the corresponding time period, the number of read commands processed in excess of a reference latency during the corresponding time period, and a throughput, and

wherein the throughput is determined based on the total size of read data requested by the read command input during each of the time periods and the time taken to process the read command.

2. The memory system of claim 1 , wherein the memory controller sets the command delay time for each of the plurality of time periods differently within a set maximum command delay time.

3. The memory system of claim 1 , wherein the memory controller sets one or more candidate command delay times for setting the target command delay time based on the throughput and the number of read commands processed in excess of the reference latency for each of the plurality of time periods.

4. The memory system of claim 3 , wherein the memory controller

selects N time periods having the highest throughput from among the plurality of time periods, and

sets M command delay times set in M time periods in which the number of read commands processed in excess of the reference latency is the smallest among the N time periods as the candidate command delay times, and

wherein N is a natural number greater than or equal to 2, and M is a natural number less than or equal to N.

5. The memory system of claim 4 , wherein the memory controller sets, among the M candidate command delay times, the candidate command delay time having the lowest ratio of the number read requests input to the memory device to the total number of read commands received during corresponding time period as the target command delay time.

6. An operating method of a memory system including a memory device comprising:

executing a read operation by setting a command delay time, which is time for determining whether to merge and process read commands, for each of a plurality of time periods; and

setting a target command delay time, from among the command delay times set for each of the plurality of time periods, to be used for determining whether to merge and process a subsequent read command with one or more previous commands based on the execution result of the read operation for each of the plurality of time periods,

wherein data requested by read commands inputted during the command delay time is processed simultaneously when the read commands are merged and processed,

wherein read commands inputted during each of the plurality of time periods is merged and processed based on the command delay time set for the each of the plurality of time periods, and

wherein the execution result of the read operation for each of the plurality of time periods includes the number of read commands input during the corresponding time period, the number of read requests input to the memory device during the corresponding time period, the number of read commands processed in excess of a reference latency during the corresponding time period, and a throughput, and

wherein the throughput is determined based on the total size of read data requested by the read command input during each of the time periods and the time taken to process the read command.

7. The operating method of claim 6 , wherein the command delay times for each of the plurality of time periods are set differently within a set maximum command delay time.

8. The operating method of claim 6 , wherein setting the target command delay time comprises setting one or more candidate command delay times for setting the target command delay time based on the throughput and the number of read commands processed in excess of the reference latency for each of the plurality of time periods.

9. The operating method of claim 8 , wherein setting the target command delay time comprises:

selecting N time periods having the highest throughput from among the plurality of time periods; and

setting M command delay times set in M time periods in which the number of read commands processed in excess of the reference latency is the smallest among the N time periods as the candidate command delay times, and

wherein N is a natural number greater than or equal to 2, and M is a natural number less than or equal to N.

10. The operating method of claim 9 , wherein setting the target command delay time comprises setting, among the M candidate command delay times, the candidate command delay time having the lowest ratio of the number of read requests input to the memory device to the total number of read commands received during corresponding time period as the target command delay time.