IP Library › Granted Patent US 11,676,789
Granted Patent B2
US 11,676,789 · App. 17/211,538 · Granted Jun 13, 2023

Semiconductor device

Inventors: Yoshiomi Shiina (Tokyo, JP); Kenji Yoshida (Tokyo, JP)
Assignee: ABLIC Inc.
H01H85/0241G01R31/74H03K3/037H03K19/20H01H2085/0283
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Quick Facts
Patent No.
US 11,676,789
App. No.
17/211,538
Granted
Jun 13, 2023
Kind
B2
Abstract

Provided is a semiconductor device capable of detecting an abnormal state in which two fuses are both short-circuited or cut. The semiconductor device includes: a trimming circuit having a first fuse and a second fuse connected in series; a current source circuit configured to supply current to the trimming circuit; and a determination circuit configured to determine whether a connection state or disconnect state of the first fuse and the second fuse are abnormal or not based upon signals derived from an output signal of the trimming circuit.

Claims (54)

1. A semiconductor device comprising:

a trimming circuit including a first fuse and a second fuse connected in series;

a current source circuit which is connected between a first power supply terminal supplying a first power source and a second power supply terminal supplying a second power source, and which is configured to supply current to the trimming circuit;

a determination circuit configured to determine whether a connection state or disconnect state of the first fuse and the second fuse are abnormal or not based upon signals derived from an output signal of the trimming circuit;

a first current source containing a first end to be connected to the first power supply terminal, and a second end connected to the first fuse; and

a second current source containing a first end connected to the second fuse, and a second end to be connected to a second power supply terminal,

wherein the first fuse includes a first end connected to the second end of the first current source, and a second end,

wherein the second fuse includes a first end connected to the second end of the first fuse, and a second end connected to the first end of the second current source,

wherein the current source circuit includes:

a third current source containing a first end connected to the first power supply terminal and a second end;

a fourth current source containing a first end and a second end connected to the second power supply terminal;

a first switch containing a first port connected to the second end of the third current source and a second port connected to the second end of the first fuse and the first end of the second fuse; and

a second switch containing a first port connected to the second port of the first switch, the second end of the first fuse, and the first end of the second fuse, and a second port connected to the first end of the fourth current source, and

wherein the determination circuit includes:

a latch circuit containing an input terminal connected to the second port of the first switch, the first port of the second switch, the second end of the first fuse, and the first end of the second fuse, and an output terminal; and

a logic circuit containing a first input terminal connected to the output terminal of the latch circuit, a second input terminal connected to the input terminal of the latch circuit, and an output terminal from which a signal indicative of a result of determining a match or mismatch between a signal supplied to the first input terminal and a signal supplied to the second input terminal is provided.

2. The semiconductor device according to claim 1 , further comprising a control circuit configured to generate a first control signal to control opening/closing of the first switch and a second control signal to control opening/closing of the second switch,

wherein the first switch includes a control port to which the first control signal is supplied, and

the second switch includes a control port to which the second control signal is supplied.

3. A semiconductor device comprising:

a trimming circuit including a first fuse and a second fuse connected in series;

a current source circuit which is connected between a first power supply terminal supplying a first power source and a second power supply terminal supplying a second power source, and which is configured to supply current to the trimming circuit;

a determination circuit configured to determine whether a connection state or disconnect state of the first fuse and the second fuse are abnormal or not based upon signals derived from an output signal of the trimming circuit;

a first current source containing a first end to be connected to the first power supply terminal, and a second end connected to the first fuse; and

a second current source containing a first end connected to the second fuse, and a second end to be connected to a second power supply terminal,

wherein the first fuse includes a first end connected to the second end of the first current source, and a second end,

wherein the trimming circuit further includes a first switch between the first fuse and the second fuse, the first switch containing a first port connected to the second end of the first fuse, and a second port,

wherein the second fuse includes a first end connected to the second port of the first switch, and a second end connected to the first end of the second current source,

wherein the current source circuit includes:

a third current source containing a first end connected to the first power supply terminal and a second end;

a fourth current source containing a first end and a second end connected to a second power supply terminal;

a second switch containing a first port connected to the second end of the third current source and a second port connected to the first end of the second fuse and the second port of the first switch; and

a third switch containing a first port connected to the second end of the first fuse and the first port of the first switch and a second port connected to the first end of the fourth current source, and

wherein the determination circuit is configured by a logic circuit including a first input terminal connected to the first port of the first switch, the first port of the third switch, and the second end of the first fuse, a second input terminal connected to the second port of the first switch, the second port of the second switch, and the first end of the second fuse, and an output terminal from which a signal indicative of a result of determining a match or mismatch between a signal supplied to the first input terminal and a signal supplied to the second input terminal is provided.

4. The semiconductor device according to claim 3 , further comprising a control circuit configured to generate a control signal having one signal level selected from a first signal level and a second signal level,

wherein the first switch contains a control terminal to which the control signal is supplied, and is configured to be closed in response to reception of the control signal at the first signal level and opened in response to reception of the control signal at the second signal level,

wherein the second switch includes a control terminal to which the control signal is supplied, and is configured to be opened in response to reception of the control signal at the first signal level and closed in response to reception of the control signal at the second signal level, and

wherein the third switch includes a control terminal to which the control signal is supplied, and is configured to be opened in response to reception of the control signal at the first signal level and closed in response to reception of the control signal at the second signal level.

5. The semiconductor device according to claim 3 , further comprising a control circuit configured to generate a first control signal having one signal level selected from a first signal level and a second signal level, and a second control signal having a signal level inconsistent with the selected signal level of the first control signal,

wherein the first switch includes a control port to which the first control signal is supplied, and

the second switch and the third switch each include a control port to which the second control signal is supplied.

6. A semiconductor device comprising:

a trimming circuit including a first fuse and a second fuse connected in series;

a current source circuit which is connected between a first power supply terminal supplying a first power source and a second power supply terminal supplying a second power source, and which is configured to supply current to the trimming circuit;

a determination circuit configured to determine whether a connection state or disconnect state of the first fuse and the second fuse are abnormal or not based upon signals derived from an output signal of the trimming circuit,

wherein the first fuse includes a first end and a second end,

wherein the second fuse includes a first end connected to the second end of the first fuse, and a second end,

wherein the current source circuit includes:

a first current source containing a first end to be connected to the first power supply terminal and a second end connected to the first fuse;

a second current source containing a first end connected to the second fuse and a second end to be connected to a second power supply terminal;

a third current source containing a first end connected to the first power supply terminal and a second end;

a fourth current source containing a first end and a second end connected to the second power supply terminal;

a first switch containing a first port connected to the second end of the third current source and a second port connected to the second end of the first fuse and the first end of the second fuse; and

a second switch containing a first port connected to the second port of the first switch, the second end of the first fuse, and the first end of the second fuse, and a second port connected to the first end of the fourth current source.

Assignments (2)
CHANGE OF ADDRESS Recorded Jun 8, 2023
From: ABLIC INC.
To: ABLIC INC.
Reel/Frame 064021/0575 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 25, 2021
From: SHIINA, YOSHIOMI; YOSHIDA, KENJI
To: ABLIC INC.
Reel/Frame 055717/0093 →