MITIGATION OF BRANCH MISPREDICTION PENALTY IN A HARDWARE MULTI-THREAD MICROPROCESSOR
Embodiments are provided for mitigation of branch misprediction penalty in hardware multi-thread microprocessors. In some embodiments, a hardware multi-thread microprocessor includes first stage circuitry that fetches a pair of consecutive instructions of a program executed in a thread. Such microprocessor also includes second stage circuitry that determines, during a clock cycle, that a first instruction in that pair is a branch instruction. The first stage circuitry fetches, during a second clock cycle after the clock cycle, a pair of branch target instructions of the program using a branch prediction. Such microprocessor further includes third stage circuitry that determines that the branch prediction is a misprediction during the second clock cycle. The first stage circuitry sends the second instruction to the second stage circuitry during a third clock cycle after the second clock cycle. The second stage circuitry decodes the second instruction during the third clock cycle.
1 . A multi-thread microprocessor, comprising:
first stage circuitry that fetches a pair of consecutive instructions of a program executed in a thread of multiple threads;
second stage circuitry that determines, during a clock cycle, that a first instruction in the pair of consecutive instructions is a branch instruction;
the first stage circuitry fetches, during a second clock cycle after the clock cycle, a pair of branch target instructions of the program using a branch prediction, wherein the second clock cycle follows the clock cycle without interruption; and
third stage circuitry that determines that the branch prediction is a misprediction during the second clock cycle;
the first stage circuitry sends the second instruction to the second stage circuitry during a third clock cycle after the second clock cycle, wherein the third clock cycle follows the second clock cycle without interruption; and
the second stage circuitry decodes the second instruction during the third clock cycle.
2 . The multi-thread microprocessor of claim 1 , wherein the first stage circuitry fetches a second pair of consecutive instructions of the program during a fourth clock cycle after the third clock cycle, wherein the fourth clock cycle follows the third clock cycle without interruption; and
wherein the third stage circuitry executes the second instruction during the fourth clock cycle.
3 . The multi-thread microprocessor of claim 1 , wherein the first stage circuitry comprises a fetch buffer, and wherein the first stage circuitry fetches the pair of consecutive instructions by,
receiving a doubleword address, a first word of the doubleword address defining an address of the first instruction and a second word of the doubleword address defining an address of the second instruction; and
storing the first instruction and the second instruction in the fetch buffer.
4 . The multi-thread microprocessor of claim 3 , wherein the doubleword address has a width of 64 bits or 32 bits.
5 . The multi-thread microprocessor of claim 3 , wherein the first stage circuitry fetches the pair of branch target instructions by,
receiving a second doubleword address, a first word of the second doubleword address defining an address of a first branch target instruction of the pair of branch target instructions and a second word of the second doubleword address defining an address of a second branch target instruction of the pair of target branch instructions; and
storing the first branch target instruction and the second branch target instruction in the fetch buffer.
6 . The multi-thread microprocessor of claim 4 , wherein the second doubleword address has a width of 64 bits or 32 bits.
7 . The multi-thread microprocessor of claim 1 , further comprising a branch predictor component that supplies the branch prediction.
8 . The multi-thread microprocessor of claim 7 , wherein the branch predictor component comprises one of a 1-bit branch predictor or a 2-bit branch predictor.
9 . A multi-thread microprocessor, comprising:
first stage circuitry that determines, during a clock cycle, that a first instruction of a program executed in a thread of multiple threads is a branch instruction;
second stage circuitry that fetches, during a second clock cycle after the clock cycle, a pair of branch target instructions of the program using a branch prediction, wherein the second clock cycle follows the clock cycle without interruption; and
third stage circuitry that determines that the branch prediction is a misprediction during the second clock cycle;
the first stage circuitry decodes a first instruction of the pair of branch target instructions during a third clock cycle after the second clock cycle, wherein the third clock cycle follows the second clock cycle without interruption;
the second stage circuitry fetches, during a fourth clock cycle after the third clock cycle, a pair of consecutive instructions of the program;
the second stage circuitry sends an instruction of the pair of consecutive instructions to the first stage circuitry during a fifth clock cycle after the fourth clock cycle, wherein the fifth clock cycle follows the fourth clock cycle without interruption; and
the first stage circuitry decodes the instruction of the pair of consecutive instructions during the fifth clock cycle.
10 . The multi-thread microprocessor of claim 9 , wherein the second stage circuitry comprises a fetch buffer, and wherein the second stage circuitry fetches the pair of consecutive instructions by,
receiving a doubleword address, a first word of the doubleword address defining an address of a second instruction and a second word of the doubleword address defining an address of a third instruction of the pair of consecutive instructions; and
storing the second instruction and the third instruction in the fetch buffer.
11 . The multi-thread microprocessor of claim 10 , wherein the doubleword address has a width of 64 bits or 32 bits.
12 . The multi-thread microprocessor of claim 9 , wherein the first stage circuitry fetches the pair of branch target instructions by
receiving a second doubleword address, a first word of the second doubleword address defining an address of a first branch target instruction of the pair of branch target instructions and a second word of the second doubleword address defining an address of a second branch target instruction of the pair of target branch instructions; and
storing the first branch target instruction and the second branch target instruction in the fetch buffer.
13 . The multi-thread microprocessor of claim 12 , wherein the second doubleword address has a width of 64 bits or 32 bits.
14 . The multi-thread microprocessor of claim 9 , further comprising a branch predictor component that supplies the branch prediction.
15 . A microcontroller unit, comprising:
a multi-thread microprocessor, including,
first stage circuitry that fetches a pair of consecutive instructions of a program executed in a thread;
second stage circuitry that determines, during a clock cycle, that a first instruction in the pair of consecutive instructions is a branch instruction;
the first stage circuitry fetches, during a second clock cycle after the clock cycle, a pair of branch target instructions of the program using a branch prediction, wherein the second clock cycle follows the clock cycle without interruption; and
third stage circuitry that determines that the branch prediction is a misprediction during the second clock cycle;
the first stage circuitry sends the second instruction to the second stage circuitry during a third clock cycle after the second clock cycle, wherein the third clock cycle follows the second clock cycle without interruption; and
the second stage circuitry decodes the second instruction during the third clock cycle.
16 . The microcontroller unit of claim 15 , wherein the first stage circuitry fetches a second pair of consecutive instructions of the program during a fourth clock cycle after the third clock cycle, wherein the fourth clock cycle follows the third clock cycle without interruption; and
wherein the third stage circuitry executes the second instruction during the fourth clock cycle.
17 . The microcontroller unit of claim 15 , wherein the first stage circuitry comprises a fetch buffer, and wherein the first stage circuitry fetches the pair of consecutive instructions by,
receiving a doubleword address, a first word of the doubleword address defining an address of the first instruction and a second word of the doubleword address defining an address of the second instruction; and
storing the first instruction and the second instruction in the fetch buffer.
18 . The microcontroller unit of claim 17 , wherein the doubleword address has a width of 64 bits or 32 bits.
19 . The microcontroller unit of claim 17 , wherein the first stage circuitry fetches the pair of branch target instructions by,
receiving a second doubleword address, a first word of the second doubleword address defining an address of a first branch target instruction of the pair of branch target instructions and a second word of the second doubleword address defining an address of a second branch target instruction of the pair of target branch instructions; and
storing the first branch target instruction and the second branch target instruction in the fetch buffer.
20 . The microcontroller unit of claim 18 , wherein the second doubleword address has a width of 64 bits or 32 bits.
21 . The microcontroller unit of claim 15 , further comprising a branch predictor component that supplies the branch prediction.