METHOD FOR REDUCING LOST CYCLES AFTER BRANCH MISPREDICTION IN A MULTI-THREAD MICROPROCESSOR

1 . A method, comprising:

fetching, by first stage circuitry of a multi-thread microprocessor, a pair of consecutive instructions of a program executed in a thread of multiple threads;

determining, by second stage circuitry of the multi-thread microprocessor, during a clock cycle, that a first instruction in the pair of consecutive instructions is a branch instruction;

fetching, by the first stage circuitry, during a second clock cycle after the clock cycle, a pair of branch target instructions of the program using a branch prediction, wherein the second clock cycle follows the clock cycle without interruption;

determining, by third stage circuitry of the multi-thread microprocessor, during the second clock cycle, that the branch prediction is a misprediction;

sending the second instruction from a fetch buffer to the second stage circuitry during a third clock cycle after the second clock cycle, wherein the third clock cycle follows the second clock cycle without interruption; and

decoding the second instruction by the second stage circuitry during the third clock cycle.

2 . The method of claim 1 , further comprising,

fetching, by the first stage circuitry, during a fourth clock cycle after the third clock cycle a second pair of consecutive instructions of the program; and

executing, by the third stage circuitry, the second instruction during the fourth clock cycle, wherein the fourth clock cycle follows the third clock cycle without interruption.

3 . The method of claim 1 , wherein the pair of consecutive instructions is fetched using a doubleword address, a first word of the doubleword address defining an address of the first instruction and a second word of the doubleword address defining an address of the second instruction.

4 . The method of claim 3 , further comprising storing the first instruction and the second instruction in the fetch buffer.

5 . The method of claim 3 , wherein the doubleword address has a width of 64 bits or 32 bits.

6 . The method of claim 1 , wherein the pair of branch target instructions is fetched using a second doubleword address, a first word of the second doubleword address defining an address of a first branch target instruction of the pair of branch target instructions and a second word of the second doubleword address defining an address of a second branch target instruction of the pair of target branch instructions; and

7 . The method of claim 6 , further comprising storing the first branch target instruction and the second branch target instruction in the fetch buffer.

8 . The method of claim 6 , wherein the second doubleword address has a width of 64 bits or 32 bits.

9 . The method of claim 1 , wherein the branch prediction is based on one of a 1-bit branch predictor or a 2-bit branch predictor.

10 . A method, comprising:

determining, by first stage circuitry of a multi-thread microprocessor, during a clock cycle, that a first instruction of a program executed in a thread of multiple threads is a branch instruction;

fetching, by second stage circuitry of the multi-thread microprocessor, during a second clock cycle after the clock cycle, a pair of branch target instructions of the program using a branch prediction, wherein the second clock cycle follows the clock cycle without interruption;

determining, by a third stage circuitry of the multi-thread microprocessor, during the second clock cycle, that the branch prediction is a misprediction;

decoding, by the first stage circuitry, a first instruction of the pair of branch target instructions during a third clock cycle after the second clock cycle, wherein the third clock cycle follows the second clock cycle without interruption;

fetching, by the second stage circuitry, during a fourth clock cycle after the third clock cycle, a pair of consecutive instructions of the program;

sending an instruction of the pair of consecutive instructions from a fetch buffer to the first stage circuitry during a fifth clock cycle after the fourth clock cycle, wherein the fifth clock cycle follows the fourth clock cycle without interruption; and

decoding, by the first stage circuitry, the instruction of the pair of consecutive instructions during the fifth clock cycle.

11 . The method of claim 10 , wherein the pair of consecutive instructions is fetched in a doubleword address, a first word of the doubleword address defining an address of a second instruction and a second word of the doubleword address defining an address of a third instruction of the pair of consecutive instructions.

12 . The method of claim 11 , further comprising storing the second instruction and the third instruction in the fetch buffer.

13 . The method of claim 11 , wherein the doubleword address has a width of 64 bits or 32 bits.

14 . The method of claim 11 , wherein the pair of branch target instructions is fetched using a second doubleword address.

15 . The method of claim 14 , further comprising storing the first branch target instruction and the second branch target instruction in the fetch buffer.

16 . The method of claim 14 , wherein the second doubleword address has a width of 64 bits or 32 bits.

17 . The method of claim 10 , wherein the branch prediction is based on one of a 1-bit branch predictor or a 2-bit branch predictor.