Granted Patent B2

US 11,657,018 · App. 17/215,122 · Granted May 23, 2023

Inventors: Colin Zou (San Jose, CA); Tao Chen (Beijing, CN)

Assignee: EMC IP HOLDING COMPANY LLC

G06F15/8092G06F9/44589G06F9/5044G06F9/545G06F9/546

Abstract

Claims (42)

1. A computer implemented method of data decompression and verification, comprising:

decompressing a compressed data segment to generate a decompressed data region;

generating a segment vector array (SVA) including a plurality of segment vectors corresponding to data segments within the decompressed data region, each segment vector indicating a location and a size of a corresponding data segment;

transmitting the SVA to a chain plugin module;

transmitting segment vector array data to a SVA-based message constructor;

constructing a SVA-based message including the location and size of data segments within the decompressed data region;

transmitting the SVA-based message to a hardware accelerator; and

performing a plurality of verification sessions at the hardware accelerator, each verification session corresponding to a specific data segment indicated by the SVA-based message.

2. The computer implemented method as in claim 1 , wherein the chain plugin module is located within a user space along with a filesystem responsible for generating the segment vector array.

3. The computer implemented method as in claim 2 , wherein the SVA-based message constructor is located within a kernel space along with the hardware accelerator.

4. The computer implemented method as in claim 1 , wherein the hardware accelerator performs the plurality of verification sessions in a verification sequence that is different than a sequence corresponding to the location of the data segments within the decompressed data region.

5. The computer implemented method as in claim 1 , wherein transmitting the SVA-based message to the hardware accelerator provides the hardware accelerator with a data layout of the decompressed data region.

6. The computer implemented method as in claim 5 , wherein providing the hardware accelerator with the data layout of the decompressed data region reduces a number of context switches between a user space and a kernel space.

7. The computer implemented method as in claim 5 , wherein providing the hardware accelerator with the data layout of the decompressed data region reduces a number of hardware accelerator session launches.

8. A data decompression and verification system comprising:

a hardware accelerator for decompressing data to generate a decompressed data region and performing data verification;

a filesystem configured to generate a segment vector array (SVA) including a plurality of segment vectors corresponding to data segments within the decompressed data region, each segment vector indicating a location and a size of a corresponding data segment;

a chain plugin module configured to receive the SVA from the filesystem; and

a SVA-based message constructor configured to:

receive segment vector array data from the chain plugin module;

construct a SVA-based message including the location and size of data segments within the decompressed data region; and

transmit the SVA-based message to the hardware accelerator,

wherein the hardware accelerator is further configured to perform a plurality of verification sessions, each verification session corresponding to a specific data segment indicated by the SVA-based message.

9. The data decompression and verification system as in claim 8 , wherein the chain plugin module is located within a user space along with the filesystem responsible for generating the SVA.

10. The data decompression and verification system as in claim 9 , wherein the SVA-based message constructor is located within a kernel space along with the hardware accelerator.

11. The data decompression and verification system as in claim 8 , wherein the hardware accelerator performs the plurality of verification sessions in a verification sequence that is different than a sequence corresponding to the location of the data segments within the decompressed data region.

12. The data decompression and verification system as in claim 8 , wherein transmitting the SVA-based message to the hardware accelerator provides the hardware accelerator with a data layout of the decompressed data region.

13. The data decompression and verification system as in claim 12 , wherein providing the hardware accelerator with the data layout of the decompressed data region reduces a number of context switches between a user space and a kernel space.

14. The data decompression and verification system as in claim 12 , wherein providing the hardware accelerator with the data layout of the decompressed data region reduces a number of hardware accelerator session launches.

15. A non-transitory computer-readable medium storing instructions which, when executed by one or more processors, cause the one or more processors to perform a data decompression and verification operation, the operation comprising:

decompressing a compressed data segment to generate a decompressed data region;

generating a segment vector array (SVA) including a plurality of segment vectors corresponding to data segments within the decompressed data region, each segment vector indicating a location and a size of a corresponding data segment;

transmitting the SVA to a chain plugin module;

transmitting segment vector array data to a SVA-based message constructor;

constructing a SVA-based message including the location and size of data segments within the decompressed data region;

transmitting the SVA-based message to a hardware accelerator; and

performing a plurality of verification sessions at the hardware accelerator, each verification session corresponding to a specific data segment indicated by the SVA-based message.

16. The non-transitory computer-readable medium as in claim 15 , wherein the chain plugin module is located within a user space along with a filesystem responsible for generating the segment vector array.

17. The non-transitory computer-readable medium as in claim 16 , wherein the SVA-based message constructor is located within a kernel space along with the hardware accelerator.

18. The non-transitory computer-readable medium as in claim 15 , wherein the hardware accelerator performs the plurality of verification sessions in a verification sequence that is different than a sequence corresponding to the location of the data segments within the decompressed data region.

19. The non-transitory computer-readable medium as in claim 15 , wherein transmitting the SVA-based message to the hardware accelerator provides the hardware accelerator with a data layout of the decompressed data region.

20. The non-transitory computer-readable medium as in claim 19 , wherein providing the hardware accelerator with the data layout of the decompressed data region reduces a number of context switches between a user space and a kernel space.

Assignments (10)

Continuity (1)