Method for programming a programmable gate array in a distributed computer system

1. A method for programming at least one programmable gate array in a distributed computer system, the method comprising:

providing configuration software for programming peripheral programmable gate arrays in the computer system;

integrating a first programmable gate array into a periphery of the computer system, the first programmable gate array being adapted to read out a bitstream from a first non-volatile memory and to configure a logic circuit on the first programmable gate array according to the specifications of the read-out bitstream;

providing a configuration, on the first programmable gate array, of a first configuration logic, which is configured to receive a first user bitstream from the configuration software for configuring a first user logic on the first programmable gate array, and to store the first user bitstream on the first non-volatile memory;

transmitting a first user bitstream from the configuration software to the first configuration logic via at least one data line of the computer system;

storing the first user bitstream on the first non-volatile memory by the first configuration logic;

configuring the first user logic on the first programmable gate array with the aid of the first user bitstream;

configuring, along with the first user logic, a monitoring logic on the first programmable gate array, which is configured to monitor input data fed into the first programmable gate array by the computer system and to detect a reset command in the input data for reconfiguring the first programmable gate array;

transmitting the reset command from the configuration software to the monitoring logic via at least one data line of the computer system; and

restoring an initial state, in which the first configuration logic on the first programmable gate array is configured to receive a new user bitstream from the configuration software for configuring a new user logic on the first programmable gate array and to store it on the first non-volatile memory by the monitoring logic as a result of the detection of the reset command.

2. The method according to claim 1 , wherein the first configuration logic initiates the configuration of the first user logic.

3. The method according to claim 1 ,

wherein an initial bitstream for configuring the first configuration logic on the first programmable gate array is stored on the first non-volatile memory via a dedicated programming interface of the first programmable gate array or a JTAG interface, and

wherein the first user bitstream is transmitted to the first configuration logic with the aid of a data interface of the first programmable gate array, which is not identical to the dedicated programming interface.

4. The method according to claim 1 , wherein the first configuration logic or the initial bitstream remains on the first programmable gate array after the configuration of the first user logic.

5. The method according to claim 4 ,

wherein the initial bitstream remains in a first memory slot of the first non-volatile memory and the first user bitstream remains in a second memory slot of the first non-volatile memory,

wherein the first programmable gate array reads out a bitstream from either the first memory slot or the second memory slot and configures a logic circuit on the first programmable gate array according to the specifications of the read-out bitstream, and

wherein the first programmable gate array is configured to automatically read out the bitstream stored in the first memory slot and to configure a logic circuit on the first programmable gate array according to the specifications of the bitstream stored in the first memory slot.

6. The method according to claim 1 , wherein the monitoring logic is identical to the first configuration logic.

7. The method according to claim 1 , wherein the first programmable gate array is configured to automatically configure the first configuration logic on the first programmable gate array via the initial bitstream after the computer system is switched on.

8. The method according to claim 1 , further comprising:

integrating a second programmable gate array into the periphery of the computer system, the second programmable gate array being designed to read out a bitstream from a second non-volatile memory and to configure a logic circuit on the second programmable gate array according to the specifications of the read-out bitstream;

configuring, on the second programmable gate array, a second configuration logic, which is configured to receive a second user bitstream for configuring a second user logic on the second programmable gate array and to store it on the second non-volatile memory;

configuring, on the first programmable gate array, a programming logic, which is configured to receive the second user bitstream from the configuration software and to transmit it to the second configuration logic via at least one data line of the computer system;

transmitting the second user bitstream from the configuration software to the programming logic;

transmitting the second user bitstream from the programming logic to the second configuration logic before the first user logic is configured on the first programmable gate array; and

configuring the second user logic on the second programmable gate array with the aid of the second user bitstream.

9. The method according to claim 8 , further comprising:

reading in at least one item of status data or a bus address, of the second programmable gate array by the programming logic;

restoring a status defined by the item of status data of the second programmable gate array by the programming logic after the second user logic is configured on the second programmable gate array.

10. The method according to claim 8 , wherein the programming logic is identical to the first configuration logic.

11. The method according to claim 8 , wherein the first configuration logic and the second configuration logic are identical with regard to their functionalities.

12. A non-transitory storage medium storing therein an initial bitstream of a programmable gate array to configure a logic circuit on the programmable gate array, which implements a configuration logic configured to carry out a method comprising:

receiving a configuration software for programming the programmable gate array;

receiving a user bitstream at a data interface of the programmable gate array for configuring a user logic on the programmable gate array;

storing the user bitstream on a non-volatile memory of the programmable gate array;

configuring the user logic on the programmable gate array via the user bitstream;

configuring, along with the user logic, a monitoring logic on the programmable gate array, which is configured to monitor input data fed into the programmable gate array by a computer system and to detect a reset command in the input data for reconfiguring the programmable gate array;

transmitting the reset command from the configuration software to the monitoring logic via at least one data line of a computer system; and

restoring an initial state, in which the configuration logic on the programmable gate array is configured to receive a new user bitstream from the configuration software for configuring a new user logic on the programmable gate array and to store it on the non-volatile memory by the monitoring logic as a result of the detection of the reset command.

13. The non-transitory storage medium according to claim 12 , wherein the method carried out by the configuration logic further comprises:

generating the initial bitstream in a programming environment for programming programmable gate arrays, designed as a block which is integratable into a graphical program.

14. A method for programming at least one programmable gate array in a distributed computer system, the method comprising:

providing configuration software for programming peripheral programmable gate arrays in the computer system;

integrating a first programmable gate array into a periphery of the computer system, the first programmable gate array being adapted to read out a bitstream from a first non-volatile memory and to configure a logic circuit on the first programmable gate array according to the specifications of the read-out bitstream;

providing a configuration, on the first programmable gate array, of a first configuration logic, which is configured to receive a first user bitstream from the configuration software for configuring a first user logic on the first programmable gate array, and to store the first user bitstream on the first non-volatile memory;

transmitting a first user bitstream from the configuration software to the first configuration logic via at least one data line of the computer system;

storing the first user bitstream on the first non-volatile memory by the first configuration logic;

configuring the first user logic on the first programmable gate array with the aid of the first user bitstream;

integrating a second programmable gate array into the periphery of the computer system, the second programmable gate array being designed to read out a bitstream from a second non-volatile memory and to configure a logic circuit on the second programmable gate array according to the specifications of the read-out bitstream;

configuring, on the second programmable gate array, a second configuration logic, which is configured to receive a second user bitstream for configuring a second user logic on the second programmable gate array and to store it on the second non-volatile memory;

configuring, on the first programmable gate array, a programming logic, which is configured to receive the second user bitstream from the configuration software and to transmit it to the second configuration logic via at least one data line of the computer system;

transmitting the second user bitstream from the configuration software to the programming logic;

transmitting the second user bitstream from the programming logic to the second configuration logic before the first user logic is configured on the first programmable gate array; and

configuring the second user logic on the second programmable gate array with the aid of the second user bitstream.

15. The method according to claim 14 , further comprising:

reading in at least one item of status data or a bus address, of the second programmable gate array by the programming logic;

restoring a status defined by the item of status data of the second programmable gate array by the programming logic after the second user logic is configured on the second programmable gate array.

16. The method according to claim 14 , wherein the programming logic is identical to the first configuration logic.

17. The method according to claim 14 , wherein the first configuration logic and the second configuration logic are identical with regard to their functionalities.