Semiconductor device and method for forming the same

1. A device comprising:

a substrate having a first side and a second side; and

a memory device, comprising:

a transistor disposed over the first side of the substrate, wherein the transistor comprises a gate and a source feature and a drain feature interposing the gate;

first conductive lines disposed over the transistor;

a memory stack disposed over the first conductive lines; and

second conductive lines disposed over the second side of the substrate, wherein at least one of the second conductive lines is a source line or a word line of the memory device.

2. The device of claim 1 , wherein the memory stack comprises a magnetic tunnel junction layer and a spin orbital torque layer.

3. The device of claim 1 , wherein the transistor comprises a fin field-effect transistor or a gate-all-around field-effect transistor.

4. The device of claim 1 , wherein the gate is a word line of the memory device.

5. The device of claim 1 , wherein at least one of the first conductive lines is a source line of the memory device.

6. A device comprising:

a substrate having a first side and a second side;

a first transistor disposed on the first side, wherein the first transistor comprises a first gate over a first protrusion, and a first source feature and a first drain feature on respective sides of the first gate;

a first buried contact disposed adjacent to the first protrusion and having at least a portion extending into the substrate, wherein the first buried contact is electrically connecting to the first source feature or the first gate;

first conductive lines disposed over the first transistor;

a memory stack of a memory device, the memory stack electrically connected to the first transistor; and

second conductive lines disposed over the second side of the substrate, wherein at least one of the second conductive lines is a source line or a word line of the memory device.

7. The device of claim 6 , further comprising:

a first contact plug disposed over the first drain feature, the first contact plug electrically connecting the first drain feature and at least one of the first conductive lines.

8. The device of claim 6 , further comprising:

a first via penetrating through the substrate and connecting to the first buried contact.

9. The device of claim 8 , wherein the first via electrically connects the second conductive lines to the first buried contact.

10. The device of claim 6 , wherein the device has a cell region and a routing region, and the first transistor and the memory stack are disposed in the cell region.

11. The device of claim 10 , further comprising:

a second transistor disposed in the routing region, wherein the second transistor comprises a second gate interposed between a second source feature and a second drain feature, wherein the second transistor is electrically connected to the first transistor by at least the second conductive lines.

12. The device of claim 11 , further comprising a third contact plug disposed over the second source feature or the second drain feature and electrically connecting the second source feature or the second drain feature to the first conductive lines.

13. The device of claim 11 , further comprising:

a second buried contact having a portion extending into the substrate and electrically connected to the second source feature, the second drain feature, or a combination thereof.

14. The device of claim 13 , further comprising a fourth contact plug disposed over the second source feature or the second drain feature when the second buried contact is electrically connected to the one of the second source feature and the second drain feature, wherein the fourth contact plug is electrically connected the one of the second source feature and the second drain feature to the second buried contact; and

a second via penetrating through the substrate and connecting to the second buried contact, wherein the second via is electrically connected to the second conductive lines.

15. The device of claim 6 , wherein the first conductive lines are arranged in two adjacent columns that columns are misaligned to each other in a direction along the columns.

16. The device of claim 6 , wherein the first conductive lines are arranged in two adjacent columns, wherein the two adjacent columns partially overlap in a direction perpendicular to the columns.

17. The device of claim 6 wherein the memory stack is disposed over the first conductive lines.

18. The device of claim 8 , wherein the memory stack is disposed over the second side of the substrate, and wherein the memory stack is electrically connected to the first transistor at least by the first buried contact and the first via.

19. A device comprising:

a substrate having a first side and a second side; and

a memory device, comprising:

a transistor disposed over the first side of the substrate, wherein the transistor comprises a gate and a source feature and a drain feature interposing the gate;

first conductive lines disposed over the transistor;

a magnetic tunnel junction memory stack disposed over the first conductive lines; and

second conductive lines disposed over the second side of the substrate, wherein at least one of the second conductive lines is a source line or a word line of the memory device.

20. The device of claim 19 , wherein the magnetic tunnel junction memory stack includes a pinning layer, a pinned layer over the pinning layer, a tunnel layer over the pinned layer, and a free layer over the tunnel layer.