IP Library Granted Patent US 11,451,129
Granted Patent B1
US 11,451,129 · App. 17/220,976 · Granted Sep 20, 2022

Gate driver circuit for a power supply voltage converter

Inventors: Robert Ryan (Cork, IE); Diarmuid Hogan (Youghal, IE)
Assignee: AES Global Holdings PTE Ltd.
H02M1/08H02M3/156
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Quick Facts
Patent No.
US 11,451,129
App. No.
17/220,976
Granted
Sep 20, 2022
Kind
B1
Abstract

A gate driver circuit comprises an auxiliary winding, a voltage summer, an auxiliary voltage bus, a gate driver integrated circuit (IC), and a controller. The auxiliary winding is positioned adjacently to the inductor and configured to inductively couple with the inductor. The voltage summer comprises a pair of diodes coupled to the auxiliary winding and a pair of capacitors coupled to the pair of diodes. The auxiliary voltage bus is configured to receive a summed voltage from the voltage summer based on a sum of voltages stored in the pair of capacitors. The gate driver IC is configured to receive a voltage from a positive rail of the auxiliary voltage bus and to output a gate control signal to control a switching device based on the received voltage and based on a pulse signal generated by the controller.

Claims (87)

1. A gate driver circuit for a voltage converter having a voltage input, a voltage output, a switching device coupled to the voltage input, and an inductor coupled between the switching device and the voltage output, the gate driver circuit comprising:

an auxiliary winding positioned adjacently to the inductor and configured to inductively couple with the inductor;

a voltage summer comprising:

a pair of diodes coupled to the auxiliary winding; and

a pair of capacitors coupled to the pair of diodes;

an auxiliary voltage bus coupled in parallel with the voltage summer and configured to receive a summed voltage from the voltage summer based on a sum of voltages stored in the pair of capacitors;

a gate driver integrated circuit (IC) coupled to the auxiliary voltage bus, the gate driver IC comprising:

a logic input configured to receive a pulse signal;

an output stage supply input configured to receive a voltage from a positive rail of the auxiliary voltage bus; and

a drive output configured to output a gate control signal based on the voltage received from the positive rail and based on the pulse signal received at the logic input; and

a controller configured to:

generate the pulse signal; and

supply the pulse signal to the logic input.

2. The gate driver circuit of claim 1 , wherein the auxiliary winding comprises a tapped winding.

3. The gate driver circuit of claim 2 , wherein the tapped winding is a center-tapped winding.

4. The gate driver circuit of claim 2 , wherein a first auxiliary winding is formed between a first end of the auxiliary winding and the tapped winding; and

wherein a second auxiliary winding is formed between a second end of the auxiliary winding and the tapped winding.

5. The gate driver circuit of claim 4 , wherein:

the pair of diodes comprises a first diode and a second diode;

the pair of capacitors comprises a first capacitor and a second capacitor;

the first diode is coupled between the first end of the first auxiliary winding and a first terminal of the first capacitor;

the second diode is coupled between the second end of the first auxiliary winding and a first terminal of the second capacitor; and

a second terminal of the first capacitor and a second terminal of the second capacitor are coupled together and to the tapped winding.

6. The gate driver circuit of claim 5 , wherein:

the first and second auxiliary windings, are configured to:

generate a first auxiliary voltage in response to a first inductor voltage generated in the inductor; and

generate a second auxiliary voltage in response to a second inductor voltage generated in the inductor;

the first capacitor is configured to store a first charge voltage in response to the first auxiliary voltage being generated in the first auxiliary winding; and

the second capacitor is configured to store a second charge voltage in response to the second auxiliary voltage being generated in the second auxiliary winding.

7. The gate driver circuit of claim 1 , wherein the gate driver circuit further comprises a switching startup circuit coupled to the auxiliary voltage bus and configured to provide a startup voltage to the auxiliary voltage bus prior to the auxiliary voltage bus receiving the summed voltage.

8. The gate driver circuit of claim 7 , wherein the switching startup circuit comprises:

a first terminal coupled to the positive rail of the auxiliary voltage bus;

a second terminal coupled to a negative rail of the auxiliary voltage bus;

a first diode coupled to the first terminal;

a second diode coupled to the first diode at a first node and coupled to the second terminal; and

a resistor coupled to the first node and configured to receive a voltage based on an input voltage received by the voltage input.

9. The gate driver circuit of claim 8 , wherein the switching start-up circuit further comprises an enable circuit coupled between the resistor and the voltage input.

10. The gate driver circuit of claim 9 , wherein the enable circuit comprises:

a switching device coupled between the resistor and the voltage input; and

a control network coupled to the switching device and configured to control switching of the switching device into conducting and non-conducting states, the control network comprising:

a resistor divider coupled to a control terminal of the switching device;

a switching device coupled to the resistor divider; and

an enable input configured to receive a signal for controlling the switching device into an on state or into an off state.

11. The gate driver circuit of claim 8 , wherein the second diode comprises a Zener diode.

12. A voltage converter comprising:

a voltage input configured to receive a bulk voltage;

a voltage output configured to provide an output voltage to a load;

a controlled switching device coupled to the voltage input;

a transformer comprising:

a primary winding coupled between the controlled switching device and the voltage output; and

a secondary winding inductively coupled with the primary winding;

a voltage summer comprising:

first and second diodes coupled to the secondary winding; and

first and second capacitors coupled to the first and second diodes;

an auxiliary voltage bus coupled in parallel with the voltage summer and configured to receive a summed voltage from the voltage summer based on a sum of voltages stored in the first and second capacitors;

a gate driver integrated circuit (IC) coupled to the auxiliary voltage bus and configured to control a conducting state of the controlled switching device based on a voltage from a positive rail of the auxiliary voltage bus and based on a pulse signal received by a logic input; and

a controller configured to:

generate the pulse signal; and

supply the pulse signal to the logic input.

13. The voltage converter of claim 12 , wherein the secondary winding comprises a center-tapped winding;

wherein a first auxiliary winding is formed between a first end of the secondary winding and the center-tapped winding; and

wherein a second auxiliary winding is formed between a second end of the secondary winding and the center-tapped winding.

14. The voltage converter of claim 13 , wherein:

the first diode is coupled between the first end of the first auxiliary winding and a first terminal of the first capacitor;

the second diode is coupled between the second end of the first auxiliary winding and a first terminal of the second capacitor; and

a second terminal of the first capacitor and a second terminal of the second capacitor are coupled together and to the center-tapped winding.

15. The voltage converter of claim 14 , wherein:

the first and second auxiliary windings, are configured to:

generate a first auxiliary voltage in response to a first inductor voltage generated in the primary winding; and

generate a second auxiliary voltage in response to a second inductor voltage generated in the primary winding;

the first capacitor is configured to store a first charge voltage in response to the first auxiliary voltage being generated in the first auxiliary winding; and

the second capacitor is configured to store a second charge voltage in response to the second auxiliary voltage being generated in the second auxiliary winding.

16. The voltage converter of claim 12 , wherein the gate driver circuit further comprises a switching startup circuit coupled to the auxiliary voltage bus and configured to provide a startup voltage to the auxiliary voltage bus prior to the auxiliary voltage bus receiving the summed voltage.

17. The voltage converter of claim 16 , wherein the switching startup circuit comprises:

a first terminal coupled to the positive rail of the auxiliary voltage bus;

a second terminal coupled to a negative rail of the auxiliary voltage bus;

a first diode coupled to the first terminal;

a second diode coupled to the first diode at a first node and coupled to the second terminal; and

a resistor coupled to the first node and configured to receive a voltage based on an input voltage received by the voltage input.

18. The voltage converter of claim 17 , wherein the switching start-up circuit further comprises an enable circuit coupled between the resistor and the voltage input, the enable circuit comprising:

a switching device coupled between the resistor and the voltage input; and

a control network coupled to the switching device and configured to control switching of the switching device into conducting and non-conducting states, the control network comprising:

a resistor divider coupled to a control terminal of the switching device;

a switching device coupled to the resistor divider; and

an enable input configured to receive a signal for controlling the switching device into an on state or into an off state.

19. The voltage converter of claim 17 , wherein the voltage converter comprises a non-synchronous buck converter.

20. The voltage converter of claim 17 , wherein the bulk voltage is greater than 100 V.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 2, 2021
From: RYAN, ROBERT; HOGAN, DIARMUID
To: AES GLOBAL HOLDINGS PTE LTD.
Reel/Frame 055804/0506 →