METHOD AND APPARATUS TO REDUCE NAND DIE COLLISIONS IN A SOLID STATE DRIVE
Quality of Service of a multi-stream solid state drive is improved by storing data to be written to a NAND die in the solid state drive in a byte-addressable write-in-place non-volatile memory in the solid state drive in the event of a NAND die collision preventing a write to the NAND die. The data stored in the a byte-addressable write-in-place non-volatile memory is written to the NAND die when the NAND die is not busy.
1 . A solid state drive comprising:
controller circuitry to receive a command from a host system communicatively coupled to the solid state drive, the command to write data in the solid state drive, the data associated with a stream;
a plurality of NAND dies to store data, a block in one of the plurality of NAND dies assigned to the stream; and
a byte-addressable write-in-place non-volatile memory to store the data associated with the stream to be written to the block in the NAND die if the NAND die is busy.
2 . The solid state drive of claim 1 , wherein data for the stream is written directly to the block in the NAND die if the NAND die is not busy.
3 . The solid state drive of claim 1 , wherein the byte-addressable write-in-place non-volatile memory includes a chalcogenide phase change material.
4 . The solid state drive of claim 1 , wherein the byte-addressable write-in-place non-volatile memory is a volatile random access memory that is battery backed up.
5 . The solid state drive of claim 1 , further comprising:
a volatile memory to store a Logical to Physical indirection table, each entry in the Logical to Physical address indirection table storing a physical block address in which the data is stored and an identifier of a memory corresponding to the physical block address.
6 . The solid state drive of claim 5 , wherein the memory is the byte-addressable write-in-place non-volatile memory.
7 . The solid state drive of claim 5 , wherein the memory is the NAND die.
8 . A method comprising:
receiving, by controller circuitry, a command from a host system communicatively coupled to a solid state drive, the command to write data in the solid state drive, the data associated with a stream;
assigning a block in a NAND die to the stream; and
storing the data associated with the stream to be written to the block in the NAND die in a byte-addressable write-in-place non-volatile memory if the NAND die is busy.
9 . The method of claim 8 , wherein data for the stream is written directly to the block in the NAND die if the NAND die is not busy.
10 . The method of claim 8 , wherein the byte-addressable write-in-place non-volatile memory includes a chalcogenide phase change material.
11 . The method of claim 8 , wherein the byte-addressable write-in-place non-volatile memory is a volatile random access memory that is battery backed up.
12 . The method of claim 8 , further comprising:
storing a Logical to Physical address indirection table in a volatile memory, each entry in the Logical to Physical address indirection table storing a physical block address in which the data is stored and an identifier of a memory corresponding to the physical block address.
13 . The method of claim 12 , wherein the memory is the byte-addressable write-in-place non-volatile memory.
14 . The method of claim 12 , wherein the memory is the NAND die.
15 . A system comprising:
a processor; and
a solid state drive comprising:
controller circuitry to receive a command to perform an operation in the solid state drive from the processor communicatively coupled to the solid state drive, the command associated with a stream to write data in the solid state drive;
a plurality of NAND dies to store data, a block in one of the plurality of NAND dies assigned to the stream; and
a byte-addressable write-in-place non-volatile memory to store data to be written to the block in the NAND die if the NAND die is busy.
16 . The system of claim 15 , wherein data for the stream is written directly to the block in the NAND die if the NAND die is not busy.
17 . The system of claim 15 , wherein the byte-addressable write-in-place non-volatile memory includes a chalcogenide phase change material.
18 . The system of claim 15 , wherein the byte-addressable write-in-place non-volatile memory is a volatile random access memory that is battery backed up.
19 . The system of claim 15 , further comprising:
a volatile memory to store a Logical to Physical indirection table, each entry in the Logical to Physical address indirection table storing a physical block address in which the data is stored and an identifier of a memory corresponding to the physical block address.
20 . The system of claim 15 , further comprising one or more of:
a display communicatively coupled to the processor; or
a battery coupled to the processor.