Method and system for hierarchical weight-sparse convolution processing

1. A computer-implemented method, comprising:

obtaining an input tensor and a filter at a convolution layer of a neural network;

segmenting the filter into a plurality of sub-filters;

generating a hierarchical bit representation of the filter representing a plurality of non-zero weights in the filter, wherein the hierarchical bit representation comprises a first layer, the first layer comprising a plurality of bits respectively corresponding to the plurality of sub-filters in the filter, each of the plurality of bits indicating whether the corresponding sub-filter includes at least one non-zero weight; and

performing multiply-and-accumulate (MAC) operations based on the hierarchical bit representation of the filter and the input tensor.

2. The method of claim 1 , wherein the performing MAC operations comprises:

identifying, based on the hierarchical bit representation, one or more of the plurality of non-zero weights in the filter and corresponding input values in the input tensor; and

performing MAC operations on the one or more identified non-zero weights and the corresponding input values.

3. The method of claim 1 , wherein the hierarchical bit representation further comprises a second layer, the second layer comprising a plurality of key-value pairs respectively corresponding to the plurality of non-zero weights in the filter, each key-value pair comprising one of the plurality of non-zero weights as value and a channel identifier of the one of the plurality of non-zero weights as key.

4. The method of claim 3 , wherein the performing MAC operations comprises:

for each of the plurality of non-zero weights, determining a channel group index based on the first layer of the hierarchical bit representation, wherein the channel group index corresponds to a filter channel group in which the non-zero weight is located;

determining an offset of the non-zero weight within the filter channel group based on the second layer of the hierarchical bit representation;

identifying an input value in the input tensor based on the channel group index and the offset; and

performing an MAC operation based on the identified input value and the non-zero weight.

5. The method of claim 3 , wherein the hierarchical bit representation further comprises a third layer, the third layer comprising a plurality of bit-vectors respectively corresponding to a plurality of horizontal planes in each of the plurality of sub-filters, wherein each of the plurality of bit-vectors indicates whether the corresponding horizontal plane comprises at least one of the plurality of non-zero weights.

6. The method of claim 5 , wherein the performing MAC operations comprises:

for each of the plurality of non-zero weights, determining a channel group index based on the first layer of the hierarchical bit representation, wherein the channel group index corresponds to a filter channel group in which the non-zero weight is located;

determining a height index and a width index of the non-zero weight based on the third layer of the hierarchical bit representation;

determining an offset of the non-zero weight within the filter channel group based on the second layer of the hierarchical bit representation;

identifying an input value in the input tensor based on the channel group index, the height index, the width index, and the offset; and

performing an MAC operation based on the identified input value and the non-zero weight.

7. The method of claim 1 , further comprising:

pruning the filter to make each of the plurality of sub-filters has either all zero weights or a prefixed number of non-zero weights.

8. The method of claim 1 , further comprising:

obtaining a plurality of partial sums from the MAC operations; and

constructing an output tensor of the convolution layer of the neural network based on the plurality of partial sums.

9. The method of claim 1 , wherein the MAC operations are parallel processed among a plurality of processors.

10. The method of claim 1 , further comprising:

segmenting the input tensor into a plurality of sub-tensors, wherein each of the plurality of sub-tensors and each of the plurality of sub-filters have a same number of channels, and

the performing MAC operations comprises:

assigning the plurality of sub-tensors and the plurality of sub-filters to a plurality of processors for parallelly performing MAC operations.

11. A system for hierarchical weight-sparse convolution processing, comprising one or more processors and one or more non-transitory computer-readable memories coupled to the one or more processors and configured with instructions executable by the one or more processors to cause the system to perform operations comprising:

obtaining an input tensor and a filter at a convolution layer of a neural network;

segmenting the filter into a plurality of sub-filters;

generating a hierarchical bit representation of the filter representing a plurality of non-zero weights in the filter, wherein the hierarchical bit representation comprises a first layer, the first layer comprising a plurality of bits respectively corresponding to the plurality of sub-filters in the filter, each of the plurality of bits indicating whether the corresponding sub-filter includes at least one non-zero weight; and

performing multiply-and-accumulate (MAC) operations based on the hierarchical bit representation of the filter and the input tensor.

12. The system of claim 11 , wherein the performing MAC operations comprises:

identifying, based on the hierarchical bit representation, one or more of the plurality of non-zero weights in the filter and corresponding input values in the input tensor; and

performing MAC operations on the one or more identified non-zero weights and the corresponding input values.

13. The system of claim 11 , wherein the hierarchical bit representation further comprises a second layer, the second layer comprising a plurality of key-value pairs respectively corresponding to the plurality of non-zero weights in the filter, each key-value pair comprising one of the plurality of non-zero weights as value and a channel identifier of the one of the plurality of non-zero weights as key.

14. The system of claim 13 , wherein the performing MAC operations comprises:

for each of the plurality of non-zero weights, determining a channel group index based on the first layer of the hierarchical bit representation, wherein the channel group index corresponds to a filter channel group in which the non-zero weight is located;

determining an offset of the non-zero weight within the filter channel group based on the second layer of the hierarchical bit representation;

identifying an input value in the input tensor based on the channel group index and the offset; and

performing an MAC operation based on the identified input value and the non-zero weight.

15. The system of claim 13 , wherein the hierarchical bit representation further comprises a third layer, the third layer comprising a plurality of bit-vectors respectively corresponding to a plurality of horizontal planes in each of the plurality of sub-filters, wherein each of the plurality of bit-vectors indicates whether the corresponding horizontal plane comprises at least one of the plurality of non-zero weights.

16. A non-transitory computer-readable storage medium for hierarchical weight-sparse convolution processing, configured with instructions executable by one or more processors to cause the one or more processors to perform operations comprising:

obtaining an input tensor and a filter at a convolution layer of a neural network;

segmenting the filter into a plurality of sub-filters;

generating a hierarchical bit representation of the filter representing a plurality of non-zero weights in the filter, wherein the hierarchical bit representation comprises a first layer, the first layer comprising a plurality of bits respectively corresponding to the plurality of sub-filters in the filter, each of the plurality of bits indicating whether the corresponding sub-filter includes at least one non-zero weight; and

performing multiply-and-accumulate (MAC) operations based on the hierarchical bit representation of the filter and the input tensor.

17. The non-transitory computer-readable storage medium of claim 16 , wherein the performing MAC operations comprises:

identifying, based on the hierarchical bit representation, one or more of the plurality of non-zero weights in the filter and corresponding input values in the input tensor; and

performing MAC operations on the one or more identified non-zero weights and the corresponding input values.

18. The non-transitory computer-readable storage medium of claim 16 , wherein the hierarchical bit representation further comprises a second layer, the second layer comprising a plurality of key-value pairs respectively corresponding to the plurality of non-zero weights in the filter, each key-value pair comprising one of the plurality of non-zero weights as value and a channel identifier of the one of the plurality of non-zero weights as key.

19. The non-transitory computer-readable storage medium of claim 18 , wherein the performing MAC operations comprises:

for each of the plurality of non-zero weights, determining a channel group index based on the first layer of the hierarchical bit representation, wherein the channel group index corresponds to a filter channel group in which the non-zero weight is located;

determining an offset of the non-zero weight within the filter channel group based on the second layer of the hierarchical bit representation;

identifying an input value in the input tensor based on the channel group index and the offset; and

performing an MAC operation based on the identified input value and the non-zero weight.

20. The non-transitory computer-readable storage medium of claim 18 , wherein the hierarchical bit representation further comprises a third layer, the third layer comprising a plurality of bit-vectors respectively corresponding to a plurality of horizontal planes in each of the plurality of sub-filters, wherein each of the plurality of bit-vectors indicates whether the corresponding horizontal plane comprises at least one of the plurality of non-zero weights.