Index space mapping using static code analysis

1. A method for computing, comprising:

providing software source code defining a processing pipeline including multiple, sequential stages of parallel computations, which include at least a first processing stage in which a first plurality of producer processors compute and output data to respective locations in a buffer and a second processing stage in which one or more consumer processors read the data from the buffer and apply a computational task to the data read from the buffer;

applying a static code analysis to the software source code so as to break the computational task into multiple, independent work units, and to define an index space in which the work units are identified by respective indexes;

based on the static code analysis, computing mapping parameters that define a mapping between the index space and addresses in the buffer, indicating by the mapping the respective ranges of the data to which the work units are to be applied;

compiling the source code so that the one or more consumer processors execute the work units identified by the respective indexes while accessing the data in the buffer in accordance with the mapping;

scheduling execution of the compiled source code responsively to the mapping; and

executing the stages in the processing pipeline in accordance with the scheduling,

wherein executing the stages comprises signaling the one or more consumer processors to begin the execution of each of the work units upon receiving an indication from the first processing stage that a respective range of the data has been output to the buffer, such that at least one of the work units begins execution by at least one of the consumer processors before all the producer processors have completed the first processing stage and outputted the data to the respective locations in the buffer.

2. The method according to claim 1 , wherein applying the static code analysis comprises evaluating ranges of variables defined by the source code, and defining the index space responsively to the evaluated ranges.

3. The method according to claim 2 , wherein evaluating the ranges comprises applying a scalar evolution technique to evaluate the ranges.

4. The method according to claim 1 , wherein the data in the buffer define a multidimensional tensor, and wherein the indexes in the defined index space have multiple index dimensions corresponding to the multidimensional tensor.

5. The method according to claim 4 , wherein computing the mapping parameters comprises defining a multidimensional transformation between the addresses in the buffer and the index space.

6. The method according to claim 5 , wherein the multi-dimensional transformation applies different, respective coefficients to transform different dimensions of the buffer.

7. The method according to claim 1 , wherein computing the mapping parameters comprises defining a linear transformation between values in the index space and the addresses in the buffer.

8. The method according to claim 7 , wherein defining the linear transformation comprises identifying a stride of a memory access operation in a program loop defined by the source code, and setting a coefficient of the linear transformation responsively to the stride.

9. The method according to claim 8 , wherein defining the linear transformation comprises defining a first linear transformation between the values in the index space and the addresses in an input buffer of the second processing stage responsively to a load operation, and

wherein the method comprises defining a second linear transformation, different from the first linear transformation, between the values in the index space and an address space of an output buffer of the second processing stage responsively to a store operation.

10. The method according to claim 1 , wherein at least the first processing stage comprises a tensor convolution operation.

11. Computing apparatus, comprising:

a memory configured to store software source code defining a processing pipeline including multiple, sequential stages of parallel computations, which include at least a first processing stage in which a first plurality of producer processors compute and output data to respective locations in a buffer and a second processing stage in which one or more consumer processors read the data from the buffer and apply a computational task to the data read from the buffer;

a processor, which is configured to apply a static code analysis to the software source code so as to break the computational task into multiple, independent work units, and to define an index space in which the work units are identified by respective indexes, and to compute, based on the static code analysis, mapping parameters that define a mapping between the index space and addresses in the buffer, indicating by the mapping the respective ranges of the data to which the work units are to be applied, and to compile the source code so that the one or more consumer processors execute the work units identified by the respective indexes while accessing the data in the buffer in accordance with the mapping;

a scheduler, which is configured to schedule execution of the compiled source code by the producer and consumer processors responsively to the mapping, and to signal the one or more consumer processors to begin the execution of each of the work units upon receiving an indication from the first processing stage that a respective range of the data has been output to the buffer, such that at least one of the work units begins execution by at least one of the consumer processors before all the producer processors have completed the first processing stage and outputted the data to the respective locations in the buffer; and

the one or more consumer processors configured to execute each of the work units based on the received signal.

12. The apparatus according to claim 11 , wherein at least the first processing stage comprises a tensor convolution operation.

13. A computer software product, comprising a tangible, non-transitory computer-readable medium in which program instructions are stored, which instructions, when read by a computer, cause the computer to perform the steps of:

providing software source code defining a processing pipeline including multiple, sequential stages of parallel computations, which include at least a first processing stage in which a first plurality of producer processors compute and output data to respective locations in a buffer and a second processing stage in which one or more consumer processors read the data from the buffer and apply a computational task to the data read from the buffer;

applying a static code analysis to the software source code so as to break the computational task into multiple, independent work units, and to define an index space in which the work units are identified by respective index;

computing, based on the static code analysis, mapping parameters that define a mapping between the index space and addresses in the buffer, indicating by the mapping the respective ranges of the data to which the work units are to be applied;

compiling the source code so that the one or more consumer processors execute the work units identified by the respective indexes while accessing the data in the buffer in accordance with the mapping;

scheduling execution of the compiled source code responsively to the mapping; and

executing the stages in the processing pipeline in accordance with the scheduling,

wherein executing the stages comprises signaling the one or more consumer processors to begin the execution of each of the work units upon receiving an indication from the first processing stage that a respective range of the data has been output to the buffer, such that at least one of the work units begins execution by at least one of the consumer processors before all the producer processors have completed the first processing stage and outputted the data to the respective locations in the buffer.

14. The product according to claim 13 , wherein the instructions cause the computer to apply the static code analysis so as to evaluate ranges of variables defined by the source code, and to define the index space responsively to the evaluated ranges.

15. The product according to claim 14 , wherein evaluating the ranges comprises applying a scalar evolution technique to evaluate the ranges.

16. The product according to claim 13 , wherein the data in the buffer define a multidimensional tensor, and wherein the indexes in the defined index space have multiple index dimensions corresponding to the multidimensional tensor.

17. The product according to claim 16 , wherein the instructions cause the computer to define a multidimensional transformation between the addresses in the buffer and the index space.

18. The product according to claim 17 , wherein the multi-dimensional transformation applies different, respective coefficients to transform different dimensions of the buffer.

19. The product according to claim 13 , wherein the instructions cause the computer to define a linear transformation between values in the index space and the addresses in the buffer.

20. The product according to claim 19 , wherein defining the linear transformation comprises identifying a stride of a memory access operation in a program loop defined by the source code, and setting a coefficient of the linear transformation responsively to the stride.

21. The product according to claim 20 , wherein defining the linear transformation comprises defining a first linear transformation between the values in the index space and the addresses in an input buffer of the second processing stage responsively to a load operation, and

wherein the instructions cause the computer to define a second linear transformation, different from the first linear transformation, between the values in the index space and an address space of an output buffer of the second processing stage responsively to a store operation.

22. The product according to claim 13 , wherein at least the first processing stage comprises a tensor convolution operation.