EFFICIENT HEAT-SINKING IN PIN DIODE
The thermal impedance of p-i-n diodes integrated on semiconductor-on-insulator substrates can be reduced with thermally conducting vias that shunt heat across thermal barriers such as, e.g., the thick top oxide cladding often encapsulating the p-i-n diode. In various embodiments, one or more thermally conducting vias extend from a top surface of the intrinsic diode layer to a metal structure connected to the doped top layer of the diode, and/or from that metal structure down to at least the semiconductor device layer of the substrate.
1 . A device comprising:
a substrate;
a top oxide cladding disposed above the substrate;
a p-i-n diode embedded in the top oxide cladding layer;
a metal structure electrically connected to the p-i-n diode; and
one or more thermal vias configured to shunt heat across at least a portion of the top oxide cladding from the metal structure to the substrate.
2 . The device of claim 1 , wherein the metal structure comprises a metal layer disposed above a top layer of the p-i-n diode.
3 . The device of claim 2 , wherein the one or more thermal vias extend from the metal layer to the substrate.
4 . The device of claim 2 , wherein the substrate comprises a semiconductor handle, a dielectric layer disposed on top of the handle, and a semiconductor device layer disposed on top of the dielectric layer, and wherein the one or more thermal vi as extend from the metal layer to the semiconductor device layer.
5 . The device of claim 4 , wherein a bottom layer of the p-i-n diode is electrically insulated from the semiconductor device layer by an intervening dielectric layer.
6 . The device of claim 2 , wherein the substrate comprises a semiconductor handle, a dielectric layer disposed on top of the handle, and a semiconductor device layer disposed on top of the dielectric layer, and wherein the one or more thermal vias extend from the metal layer through openings in the semiconductor device layer partially through the dielectric layer.
7 . The device of claim 6 , wherein the openings in the semiconductor device layer are filled with dielectric material insulating the one or more thermal vias from the semiconductor device layer.
8 . The device of claim 2 , wherein a total cross-sectional area of the one or more thermal vias in a plane parallel to a plane of the substrate exceeds an area of heat generation in the p-i-n diode.
9 . A device comprising:
a substrate;
a top oxide cladding disposed above the substrate;
embedded in the top oxide cladding, a p-i-n diode comprising an intrinsic layer;
a metal structure electrically connected to the p-i-n diode; and
one or more thermal vias configured to shunt heat across at least a portion of the top oxide cladding from the intrinsic layer to the metal structure.
10 . The device of claim 9 , wherein the metal structure comprises a metal layer disposed above a top layer of the p-i-n diode.
11 . The device of claim 10 , wherein the p-i-n diode comprises an intrinsic layer between doped bottom and top layers, and wherein the one or more thermal vias extend from the intrinsic layer to the metal layer.
12 . The device of claim 11 , wherein the p-i-n diode decreases in width from the doped bottom layer to the intrinsic layer and from the intrinsic layer to the doped top layer, and wherein the one or more thermal vias are placed on top of the intrinsic layer to one or both sides of the doped top layer.
13 . The device of claim 9 , further comprising one or more thermal vias configured to shunt heat from the metal structure to the substrate.
14 . A method comprising:
forming a p-i-n diode embedded within a top oxide cladding on a substrate, the p-i-n diode comprising doped top and bottom layers and an intrinsic layer therebetween;
etching the top oxide cladding to form electrical via holes extending down to top surfaces of the doped top and bottom layers and thermal via holes extending down to at least one of the substrate or the intrinsic layer; and
filling the electrical and thermal via holes with metal to form electrical vias for operating the p-i-n diode and one or more thermal vias for shunting heat away from the p-i-n diode.
15 . The method of claim 14 , further comprising patterning the substrate to form openings a semiconductor device layer of the substrate, wherein the thermal via holes comprises one or more via holes extending through the openings in the semiconductor device layer into a dielectric layer underneath the semiconductor device layer.
16 . The method of claim 14 , further comprising patterning the substrate to form isolation trenches surrounding the p-i-n diode in a semiconductor device layer of the substrate.
17 . The method of claim 14 , wherein electrical via holes extending down to the top surface of the doped bottom layer and thermal via holes extending down to the intrinsic layer are etched simultaneously, using the intrinsic layer as an etch stop layer for the thermal via holes.
18 . The method of claim 14 , wherein electrical via holes extending down to the top surface of the doped bottom layer and thermal via holes extending down to the substrate are etched simultaneously, using the doped bottom layer as an etch stop layer for the electrical via holes.
19 . The method of claim 14 , wherein an electrical via hole extending down to the top surface of the doped top layer is etched after one or more electrical via holes extending down to the doped bottom layer and one or more thermal via holes extending down to the intrinsic layer or the substrate have been etched.
20 . The method of claim 14 , wherein the substrate is a silicon-on-insulator substrate and the doped top and bottom layers and the intrinsic layer of the p-i-n diode are formed of III-V semiconductor material.