Method of accessing a memory, and corresponding circuit
An embodiment method of accessing a memory for reading and/or writing data comprises generating a memory transaction request comprising a burst of memory access requests towards a set of memory locations in the memory, the memory locations having respective memory addresses. The method further comprises transmitting via an interconnect bus to a memory controller circuit coupled to the memory a first signal conveying the memory transaction request and a second signal conveying information for mapping the burst of memory access requests onto respective memory addresses of the memory locations in the memory. The method further comprises computing, as a function of the information conveyed by the second signal, respective memory addresses of the memory locations, and accessing the memory locations to read data from the memory locations and/or to write data into the memory locations.
1. A method of accessing a memory for reading and/or writing data, the method comprising:
generating a memory transaction request comprising a burst of memory access requests towards a set of memory locations in the memory, the memory locations having respective memory addresses;
transmitting, via an interconnect bus to a memory controller circuit coupled to the memory, a first signal conveying the memory transaction request, and a second signal conveying information for mapping the burst of memory access requests onto respective memory addresses of the memory locations in the memory, the information including a stride value indicative of a number of units of data between two successive memory locations in the burst of memory access requests; and
computing, as a function of the information conveyed by the second signal, including the stride value, respective memory addresses of the memory locations and accessing the memory locations to read data from the memory locations and/or to write data into the memory locations.
2. The method of claim 1 , wherein the interconnect bus comprises an Advanced eXtensible Interface (AXI) bus, the method comprising:
encoding the first signal and the second signal as a function of an AXI protocol for transmission via the interconnect bus; and
transmitting the second signal over an AWUSER channel and/or an ARUSER channel of the AXI bus.
3. The method of claim 1 , wherein generating the memory transaction request comprises an incremental burst of memory access requests or a wrapping burst of memory access requests.
4. The method of claim 1 , further comprising including burst type data and burst length data in the memory transaction request conveyed by the first signal.
5. The method of claim 1 , further comprising:
including data indicative of a memory access scheme in the information conveyed by the second signal; and
accessing the memory locations to read data from the memory locations and/or to write data into the memory locations as a function of the data indicative of the memory access scheme.
6. The method of claim 5 , wherein the memory access scheme is selected from: an incremental access scheme, a low-order interleaving access scheme, or an access scheme for computation of a Fast Fourier Transform algorithm.
7. The method of claim 1 , further comprising:
programming a processing circuit to process data in a plurality of subsequent processing stages; and
generating at least one memory transaction request at each of the subsequent processing stages to read data from the memory locations and/or to write data into the memory locations.
8. A circuit comprising:
a memory for storing data;
a processing circuit for processing data;
a memory controller circuit; and
an interconnect bus; coupling the memory controller circuit to the memory and the processing circuit;
wherein the processing circuit is configured to:
generate memory transaction requests comprising respective bursts of memory access requests towards a set of memory locations in the memory, the memory locations having respective memory addresses; and
transmit via the interconnect bus to the memory controller circuit first signals conveying the memory transaction requests, and second signals conveying information for mapping the bursts of memory access requests onto respective memory addresses of the memory locations in the memory, the information including a stride value indicative of a number of units of data between two successive memory locations in the burst of memory access requests; and
wherein the memory controller circuit is configured to:
compute, as a function of the information conveyed by the second signals, including the stride value, respective memory addresses of the memory locations; and
access the memory locations to read data from the memory locations for processing by the processing circuit and/or to write data processed by the processing circuit into the memory locations.
9. The circuit of claim 8 , wherein the interconnect bus comprises an Advanced eXtensible Interface (AXI) bus, and wherein the processing circuit is further configured to:
encode the first signals and the second signals as a function of an AXI protocol for transmission via the interconnect bus; and
transmit the second signals over an AWUSER channel and/or an ARUSER channel of the AXI bus.
10. The circuit of claim 8 , wherein each memory transaction request comprises an incremental burst of memory access requests or a wrapping burst of memory access requests.
11. The circuit of claim 8 , wherein each memory transaction request conveyed by the first signals includes burst type data and burst length data in.
12. The circuit of claim 8 ,
wherein the processing circuit is configured to include data indicative of a memory access scheme in the information conveyed by the second signals; and
wherein the memory controller circuit is configured to access the memory locations to read data from the memory locations and/or to write data into the memory locations as a function of the data indicative of the memory access scheme.
13. The circuit of claim 12 , wherein the memory access scheme is selected from: an incremental access scheme, a low-order interleaving access scheme, or an access scheme for computation of a Fast Fourier Transform algorithm.
14. The circuit of claim 8 ,
wherein the processing circuit is programmed to process data in a plurality of subsequent processing stages; and
wherein the processing circuit is configured to generate at least one memory transaction request at each of the subsequent processing stages to read data from the memory locations and/or to write data into the memory locations.
15. An electronic system comprising:
system interconnect network;
a central processing unit coupled to the system interconnect network;
a main system memory coupled to the system interconnect network;
a direct memory access controller coupled to the system interconnect network; and
a digital signal processor coupled to the system interconnect network, the digital signal processor comprising:
a local memory for storing data;
a local processing circuit for processing data;
a local memory controller circuit; and
a local interconnect bus; coupling the local memory controller circuit to the local memory and the local processing circuit;
wherein the local processing circuit is configured to:
generate memory transaction requests comprising respective bursts of memory access requests towards a set of memory locations in the local memory, the memory locations having respective memory addresses; and
transmit via the local interconnect bus to the local memory controller circuit first signals conveying the memory transaction requests and second signals conveying information for mapping the bursts of memory access requests onto respective memory addresses of the memory locations in the local memory, the information including a stride value indicative of a number of units of data between two successive memory locations in the burst of memory access requests; and
wherein the local memory controller circuit is configured to:
compute, as a function of the information conveyed by the second signals, including the stride value, respective memory addresses of the memory locations; and
access the memory locations to read data from the memory locations for processing by the local processing circuit and/or to write data processed by the local processing circuit into the memory locations.
16. The electronic system according to claim 15 , wherein the local interconnect bus comprises an Advanced eXtensible Interface (AXI) bus, and wherein the local processing circuit is further configured to:
encode the first signals and the second signals as a function of an AXI protocol for transmission via the local interconnect bus; and
transmit the second signals over an AWUSER channel and/or an ARUSER channel of the AXI bus.
17. The electronic system according to claim 15 , wherein each memory transaction request comprises an incremental burst of memory access requests or a wrapping burst of memory access requests.
18. The electronic system according to claim 15 , wherein each memory transaction request conveyed by the first signals includes burst type data and burst length data in.
19. The electronic system according to claim 15 ,
wherein the local processing circuit is configured to include data indicative of a memory access scheme in the information conveyed by the second signals; and
wherein the local memory controller circuit is configured to access the memory locations to read data from the memory locations and/or to write data into the memory locations as a function of the data indicative of the memory access scheme.