Etch profile control of via opening

1. A method, comprising:

forming a gate structure over a semiconductor substrate;

forming a gate dielectric cap over the gate structure;

forming source/drain contacts over the semiconductor substrate, with the gate dielectric cap between the source/drain contacts;

depositing an etch-resistant layer over the gate dielectric cap;

depositing a contact etch stop layer over the etch-resistant layer and an interlayer dielectric (ILD) layer over the contact etch stop layer;

performing a first etching process to form a via opening extending through the ILD layer and terminating prior to reaching the etch-resistant layer;

performing a second etching process to deepen the via opening such that one of the source/drain contacts is exposed, wherein the second etching process etches the etch-resistant layer at a slower etch rate than etching the contact etch stop layer, wherein the second etching process stops when a bottom of the via opening reaches a top surface of the gate dielectric cap; and

depositing a metal material to fill the deepened via opening.

2. The method of claim 1 , wherein the gate dielectric cap and the contact etch stop layer are nitride-based.

3. The method of claim 1 , wherein the gate dielectric cap is formed of a same material as the contact etch stop layer.

4. The method of claim 1 , wherein the etch-resistant layer is oxide-based.

5. The method of claim 1 , wherein the etch-resistant layer has a thickness less than a thickness of the contact etch stop layer.

6. The method of claim 1 , wherein the etch-resistant layer has a thickness less than a maximal thickness of the gate dielectric cap.

7. The method of claim 1 , wherein the etch-resistant layer has a thickness in a range from about 1 Angstroms to about 50 Angstroms.

8. The method of claim 1 , wherein the etch-resistant layer is deposited using atomic layer deposition (ALD) or plasma enhanced chemical vapor deposition (PECVD).

9. The method of claim 1 , wherein the first etching process is a plasma etching process using a plasma generated from a hydrogen-free gaseous mixture.

10. The method of claim 1 , wherein the second etching process is a plasma etching process using a plasma generated from a hydrogen-containing gaseous mixture.

11. The method of claim 10 , wherein the hydrogen-containing gaseous mixture is a mixture of a fluorine-containing gas and a hydrogen gas.

12. The method of claim 11 , wherein the fluorine-containing gas is a CHF 3 gas, a CF 4 gas, a C x H y F z gas, or a combination thereof, wherein x, y and z are greater than zero.

13. The method of claim 1 , wherein the gate dielectric cap remains substantially intact after the second etching process is completed.

14. A method, comprising:

forming a gate structure between gate spacers and over a semiconductor substrate;

etching back the gate structure to fall below top ends of the gate spacers;

forming a gate dielectric cap over the etched back gate structure;

forming a source/drain contact in contact with a sidewall of the gate dielectric cap;

depositing an etch-resistant layer over the gate dielectric cap and the source/drain contact;

depositing in sequence an etch stop layer and an interlayer dielectric (ILD) layer over the etch-resistant layer;

performing a first etching process to form a via opening extending through the ILD layer;

after the first etching process is completed, performing a second etching process to extend the via opening down to the source/drain contact, wherein after the second etching process etches through the etch-resistant layer, a sidewall profile of the via opening becomes more vertical than before etching the etch-resistant layer; and

after performing the second etching process, forming a via structure in the via opening.

15. The method of claim 14 , wherein the first etching process does not etch the etch-resistant layer.

16. The method of claim 14 , wherein the etch-resistant layer and the ILD layer are oxide-based, and the etch stop layer and the gate dielectric cap are nitride-based.

17. The method of claim 14 , wherein the second etching process uses a gas mixture with a hydrogen gas, and the first etching process is free of the hydrogen gas.

18. A method, comprising:

forming source/drain regions over a substrate;

forming a gate structure laterally between the source/drain regions;

forming gate spacers on opposite sidewalls of the gate structure;

forming a dielectric cap over the gate structure;

forming source/drain contacts over the source/drain regions, the source/drain contacts having top surfaces higher than a bottom surface of the dielectric cap;

forming an oxide-based etch-resistant layer over the dielectric cap;

forming a nitride-based etch stop layer over the oxide-based etch-resistant layer, wherein the oxide-based etch-resistant layer is separated from a top surface of one of the gate spacers by a first distance, and the oxide-based etch-resistant layer is separated from a top surface of the gate structure by a second distance greater than the first distance;

forming an interlayer dielectric (ILD) layer over the nitride-based etch stop layer; and

forming a via structure extending through the ILD layer, the nitride-based etch stop layer, and the oxide-based etch-resistant layer to electrically connect with one of the source/drain contacts.

19. The method of claim 18 , wherein the nitride-based etch stop layer is thicker than the oxide-based etch-resistant layer.

20. The method of claim 18 , wherein the oxide-based etch-resistant layer is thinner than the dielectric cap.