Clock distribution circuit and semiconductor apparatus including the same
Devices for reducing power consumption and skew for transmission of signals in a clock distribution circuit are described. A global distribution circuit is configured to divide external clock signals to generate first divided multiphase clock signals and divide one of the first divided multiphase clock signals to generate a reference clock signal. A local distribution circuit is configured to generate second divided multiphase clock signals according to a portion of the first divided multiphase clock signals and the reference clock signal.
1. A clock distribution circuit comprising:
a global distribution circuit configured to divide external clock signals to generate first divided multiphase clock signals and divide one of the first divided multiphase clock signals to generate a reference clock signal; and
a local distribution circuit configured to generate second divided multiphase clock signals according to a portion of the first divided multiphase clock signals and the reference clock signal.
2. The clock distribution circuit according to claim 1 , wherein the global distribution circuit comprises:
a first divider configured to divide the external clock signals to generate the first divided multiphase clock signals; and
a second divider configured to output, as the reference clock signal, one of signals generated by dividing the first divided multiphase clock signals.
3. The clock distribution circuit according to claim 2 , wherein the second divider is configured to convert the one of the signals generated by dividing the first divided multiphase clock signals having a current mode logic (CML) level into a signal having a complementary metal-oxide semiconductor (CMOS) level, and to output the signal having the CMOS level as the reference clock signal.
4. The clock distribution circuit according to claim 1 , wherein the global distribution circuit comprises:
a first divider configured to divide the external clock signals to generate the first divided multiphase clock signals; and
a second divider configured to divide one of the first divided multiphase clock signals and output the divided signal as the reference clock signal.
5. The clock distribution circuit according to claim 1 , wherein the local distribution circuit is configured to convert the first divided multiphase clock signals into signals having a CMOS level and output signals having the CMOS level.
6. The clock distribution circuit according to claim 1 , wherein the local distribution circuit comprises:
a plurality of converters each configured to convert the first divided multiphase clock signals, which are inputted at a CML level, into CMOS level signals and output the CMOS level signals; and
a plurality of clock generation circuits each configured to generate the second divided multiphase clock signals according to one clock generation circuit, which corresponds to each of the plurality of clock generation circuits among the reference clock signal and shifted reference clock signals, and a portion of the first divided multiphase clock signals.
7. The clock distribution circuit according to claim 6 , wherein the plurality of clock generation circuits are each configured to generate the second divided multiphase clock signals and the shifted reference clock signal by shifting the reference clock signal according to a portion of the first divided multiphase clock signals.
8. A semiconductor apparatus comprising:
a first divider configured to divide external clock signals to generate first divided multiphase clock signals;
a second divider configured to output, as a reference clock signal, one of signals generated by dividing the first divided multiphase clock signals;
a plurality of clock generation circuits each configured to generate second divided multiphase clock signals according to one clock generation circuit, which corresponds to each of the plurality of clock generation circuits among the reference clock signal and shifted reference clock signals, and a portion of the first divided multiphase clock signals; and
a plurality of input/output terminals each configured to perform data transmission and reception according to the first divided multiphase clock signals and the second divided multiphase clock signals.
9. The semiconductor apparatus according to claim 8 , wherein the second divider is configured to convert the one of the signals generated by dividing the first divided multiphase clock signals having a current mode logic (CML) level into a complementary metal-oxide semiconductor (CMOS) level signal, and to output the CMOS level signal as the reference clock signal.
10. The semiconductor apparatus according to claim 8 , further comprising:
a plurality of converters each configured to convert the first divided multiphase clock signals, which are inputted at a CML level, into CMOS level signals and output the CMOS level signals.
11. The semiconductor apparatus according to claim 8 , wherein the plurality of clock generation circuits are each configured to generate the second divided multiphase clock signals and shifted reference clock signals by shifting the reference clock signal according to a portion of the first divided multiphase clock signals.
12. The semiconductor apparatus according to claim 8 , wherein each of the plurality of input/output terminals comprises:
an input/output pad;
a transmitter configured to receive data, which is transmitted from a memory block through a data line, according to the first divided multiphase clock signals, and to output the received data to the input/output pad according to the second divided multiphase clock signals; and
a receiver configured to receive data, which is inputted to the input/output pad, according to the first divided multiphase clock signals, and to transmit the data to the memory block through the data line according to the second divided multiphase clock signals.
13. A semiconductor apparatus comprising:
a plurality of input/output terminals each configured to perform data transmission and reception according to first divided multiphase clock signals of at least 2-phase or more and second divided multiphase clock signals of at least 2-phase;
a global distribution circuit configured to divide external clock signals to generate the first divided multiphase clock signals and divide one of the first divided multiphase clock signals to generate a 1-phase reference clock signal; and
a local distribution circuit configured to generate the second divided multiphase clock signals according to a portion of the first divided multiphase clock signals and the 1-phase reference clock signal.
14. The semiconductor apparatus according to claim 13 , wherein each of the plurality of input/output terminals comprises:
an input/output pad;
a transmitter configured to receive data, which is transmitted from a memory block through a data line, according to the first divided multiphase clock signals, and to output the received data to the input/output pad according to the second divided multiphase clock signals; and
a receiver configured to receive data, which is inputted to the input/output pad, according to the first divided multiphase clock signals, and to transmit the data to the memory block through the data line according to the second divided multiphase clock signals.
15. The semiconductor apparatus according to claim 13 , wherein the global distribution circuit comprises:
a first divider configured to divide the external clock signals to generate the first divided multiphase clock signals; and
a second divider configured to output, as the reference clock signal, one of signals generated by dividing the first divided multiphase clock signals.
16. The semiconductor apparatus according to claim 15 , wherein the second divider is configured to convert one of the signals generated by dividing the first divided multiphase clock signals having a current mode logic (CML) level into a complementary metal-oxide semiconductor (CMOS) level signal, and to output the CMOS level signal as the reference clock signal.
17. The semiconductor apparatus according to claim 13 , wherein the global distribution circuit comprises:
a first divider configured to divide the external clock signals to generate the first divided multiphase clock signals; and
a second divider configured to divide one of the first divided multiphase clock signals and output the divided signal as the reference clock signal.
18. The semiconductor apparatus according to claim 13 , wherein the local distribution circuit is configured to convert the first divided multiphase clock signals into CMOS level signals and output the CMOS level signals.
19. The semiconductor apparatus according to claim 13 , wherein the local distribution circuit comprises:
a plurality of converters each configured to convert the first divided multiphase clock signals inputted at a CML level into CMOS level signals and output the CMOS signals; and
a plurality of clock generation circuits each configured to generate the second divided multiphase clock signals according to one clock generation circuit, which corresponds to each of the plurality of clock generation circuits among the reference clock signal and shifted reference clock signals, and a portion of the first divided multiphase clock signals.
20. The semiconductor apparatus according to claim 19 , wherein the plurality of clock generation circuits are each configured to generate the second divided multiphase clock signals and the shifted reference clock signal by shifting the reference clock signal according to some of the first divided multiphase clock signals.