Memory device including pass transistor circuit
A memory device includes; a memory cell array including a first memory block and a second memory block adjacently disposed in a first direction, driving signal lines respectively corresponding to vertically stacked word lines, and a pass transistor circuit including an odd number of pass transistor groups and connected between the driving signal lines and the memory cell array. One of the odd number of pass transistor groups includes a first pass transistor connected between a first word line of the first memory block and a first driving signal line among the driving signal lines, and a second pass transistor connected between a first word line of the second memory block and the first driving signal line adjacently disposed to the first pass transistor in a second direction.
1. A memory device comprising:
a memory cell array including a first memory block and a second memory block adjacently disposed in a first direction;
driving signal lines respectively corresponding to vertically stacked word lines; and
a pass transistor circuit including an odd number of pass transistor groups and connected between the driving signal lines and the memory cell array,
wherein one of the odd number of pass transistor groups includes a first pass transistor connected between a first word line of the first memory block and a first driving signal line among the driving signal lines, and a second pass transistor connected between a first word line of the second memory block and the first driving signal line adjacently disposed to the first pass transistor in a second direction.
2. The memory device of claim 1 , wherein the first word line of the first memory block and the first word line of the second memory block are disposed at a same level.
3. The memory device of claim 1 , wherein a size of the pass transistor circuit in the first direction is substantially the same as a size of the first memory block and the second memory block in the first direction.
4. The memory device of claim 1 , wherein the odd number of pass transistor groups further comprises:
a first pass transistor group including third pass transistors respectively connected to word lines of the first memory block and disposed in the second direction;
a second pass transistor group including fourth pass transistors respectively connected to word lines of the second memory block and disposed in the second direction; and
a third pass transistor group including the first pass transistor and the second pass transistor.
5. The memory device of claim 4 , wherein the second pass transistor group is adjacently disposed in the first direction to the first pass transistor group, and
a pass transistor connected to a second word line of the first memory block among the third pass transistors and a pass transistor connected to a second word line of the second memory block among the fourth pass transistors share an active area connected to a second driving signal line among the driving signal lines.
6. The memory device of claim 4 , wherein the third pass transistor group is disposed between the first pass transistor group and the second pass transistor group.
7. The memory device of claim 4 , wherein the memory cell array further includes
a third memory block adjacently disposed in the first direction to the second memory block, and a fourth memory block adjacently disposed in the first direction to the third memory block, and
the pass transistor circuit further includes a fourth pass transistor group, a fifth pass transistor group, and a sixth pass transistor group, wherein the fourth pass transistor group includes a fifth pass transistor connected between a first word line of the third memory block and the first driving signal line, and a sixth pass transistor connected between a first word line of the fourth memory block and the first driving signal line, and adjacently disposed in the second direction to the fifth pass transistor.
8. The memory device of claim 7 , wherein the third pass transistor group is adjacently disposed in the first direction to the fourth pass transistor group, and
the first pass transistor and the sixth pass transistor share an active area connected to the first driving signal line.
9. The memory device of claim 7 , wherein the fifth pass transistor group includes a seventh pass transistors respectively connected to word lines of the third memory block and disposed in the second direction,
the sixth pass transistor group includes eighth pass transistors respectively connected to word lines of the fourth memory block and disposed in the second direction,
the fifth pass transistor group is adjacently disposed in the first direction to the sixth pass transistor group, and
a pass transistor connected to a second word line of the third memory block among the seventh pass transistors, and a pass transistor connected to a second word line of the fourth memory block among the eighth pass transistors share an active area connected to a second driving signal line among the driving signal lines.
10. The memory device of claim 1 , wherein the pass transistor circuit further includes a first pass transistor circuit disposed on one side of a combination of the first memory block and the second memory block, and a second pass transistor circuit disposed on another side of the combination of the first memory block and the second memory block opposing the one side, and
each of the first pass transistor circuit and the second pass transistor circuit includes an odd number of pass transistor groups.
11. The memory device of claim 1 , wherein each of the first memory block and the second memory block includes word lines and NAND strings, each of the NAND strings including nonvolatile memory cells respectively connected to the word lines.
12. The memory device of claim 1 , wherein the pass transistor circuit is disposed below a stair-stepped area of the word lines.
13. A memory device comprising:
a first semiconductor layer including a first memory block and a second memory block disposed in a first direction, wherein the first memory block includes vertically stacked, first word lines extending in a second direction, and the second memory block includes vertically stacked second word lines extending in the second direction; and
a second semiconductor layer including a pass transistor circuit including an odd number of pass transistor groups disposed below the first semiconductor layer,
wherein one of the odd number of pass transistor groups includes;
a first pass transistor connected between a first selection word line corresponding to one of the first word lines, and a first driving signal line,
a second pass transistor connected between a second selection word line corresponding to one of the second word lines, and the first driving signal line, and
the second pass transistor is adjacently disposed to the first pass transistor in the second direction.
14. The memory device of claim 13 , wherein the first selection word line and the second selection word line are disposed at a same level.
15. The memory device of claim 13 , wherein the pass transistor circuit is disposed below a stair-stepped area of the first word lines and second word lines.
16. The memory device of claim 13 , wherein the odd number of pass transistor groups includes:
a first pass transistor group including third pass transistors respectively connected to the first word lines and disposed in the second direction;
a second pass transistor group including fourth pass transistors respectively connected to the second word lines and disposed in the second direction; and
a third pass transistor group including the first pass transistor and the second pass transistor.
17. The memory device of claim 16 , wherein the first pass transistor group and the second pass transistor group are adjacently disposed in the first direction, and
a pass transistor connected to one of the first word lines among the third pass transistors and a pass transistor connected to one of the second word lines among the fourth pass transistors share an active area connected to a second driving signal line.
18. A memory device comprising:
a memory cell area including a first metal pad and a first memory block and a second memory block adjacently disposed in a first direction; and
a peripheral circuit area including a second metal pad and vertically connected to the memory cell area by the first metal pad and the second metal pad, and further including a pass transistor circuit including a first pass transistor group, a second pass transistor group, and a third pass transistor group adjacently disposed in the first direction,
wherein one of the first pass transistor group, the second transistor group and the third pass transistor group includes; a first pass transistor connected to a first word line of the first memory block, and a second pass transistor connected to a second word line of the second memory block and adjacently disposed to the first pass transistor in a second direction, and
the first word line of the first memory block and the first word line of the second memory block are disposed at a same level.
19. The memory device of claim 18 , wherein the first word line of the first memory block and the first word line of the second memory block are disposed at a same level, and
the pass transistor circuit is disposed below a stair-stepped area of the first word line and the second word line.
20. The memory device of claim 18 , wherein the memory cell area is formed on a first wafer, and the peripheral circuit area is formed on a second wafer.