Error correction circuit of semiconductor memory device and semiconductor memory device including the same

1. An error correction circuit of a semiconductor memory device, comprising:

an error correction code (ECC) encoder configured to:

generate, based on a first main data obtained by selectively shifting data bits of a main data based on a least significant bit (LSB) of a row address, a parity data using an ECC represented by a generation matrix, and

store a codeword including the main data and the parity data in a target page of a memory cell array; and

an ECC decoder configured to:

read the main data and the parity data from the target page,

generate a syndrome based on a second main data obtained by selectively shifting data bits of the main data based on the LSB of the row address, the parity data and a parity check matrix based on the ECC, and

correct a single bit error when the single bit error exists in the main data or to correct two bit errors when the two bit errors occur in adjacent two memory cells in the target page based on the syndrome,

wherein data bits of the main data are divided into a plurality of sub data units,

wherein the ECC includes a plurality of column vectors divided into a plurality of code groups corresponding to respective ones of the plurality of sub data units,

wherein the plurality of column vectors have elements configured to gather a mis-corrected bit and multiple error bits in one symbol, and

wherein the mis-corrected bit is generated when the multiple error bits are present in the main data.

2. The error correction circuit of claim 1 , wherein the one symbol includes two adjacent sub data units of the plurality of sub data units, and

wherein the plurality of column vectors have elements configured to place the mis-corrected bit in sub data units corresponding to the one symbol or have elements such that a column vector corresponding to the mis-corrected bit is not the same as each of the plurality of column vectors.

3. The error correction circuit of claim 2 , wherein the multiple error bits include two error bits or three or more error bits which are not adjacent to each other and are present in the one symbol.

4. The error correction circuit of claim 1 , further comprising:

a first cyclic shifter configured to generate the first main data by cyclic-shifting the data bits of the main data in a first direction in response to the LSB of the row address having a high level to provide the first main data to the ECC encoder;

a second cyclic shifter configured to generate the second main data by cyclic-shifting the data bits of the read main data in the first direction in response to the LSB of the row address having a high level to provide the second main data to the ECC decoder; and

a cyclic de-shifter configured to cyclic-shift an output data of the ECC decoder in a second direction opposite to the first direction in response to the LSB of the row address having a high level.

5. The error correction circuit of claim 1 , wherein the ECC decoder is configured to:

correct the single bit error in the main data based on a parity check matrix, and

correct the two bit errors in the main data based on a sub parity check matrix generated based on the parity check matrix.

6. The error correction circuit of claim 5 , wherein the parity check matrix includes a plurality of column vectors divided into a plurality of code groups corresponding to the plurality of sub data units and the parity data.

7. The error correction circuit of claim 6 , wherein the ECC decoder is configured to generate the sub parity check matrix by performing an exclusive OR operation on a (2i−1)-th column vector and a (2i)-th column vector adjacent to the (2i−1)-th column vector of the plurality of column vectors, i being one of 1 to k, k being a number of data bits in each of the plurality of sub data units.

8. The error correction circuit of claim 5 , wherein the ECC decoder includes:

a syndrome generation circuit configured to generate the syndrome and the sub parity check matrix based on the parity check matrix, the second main data and the parity data;

a syndrome decoding circuit configured to generate a first error decoding signal associated with the single bit error, a second error decoding signal associated with the two bit errors and a selection signal by decoding the syndrome based on the parity check matrix and the sub parity check matrix;

a first corrector configured to correct the single bit error in the second main data based on the first error decoding signal to provide a first corrected data;

a second corrector configured to correct the two bit errors in the second main data based on the second error decoding signal to provide a second corrected data; and

a selection circuit configured to select one of the second main data, the first corrected data and the second corrected data in response to the selection signal to provide the selected one as an output data of the ECC decoder.

9. The error correction circuit of claim 8 , wherein the syndrome generation circuit includes:

a syndrome generator configured to generate the syndrome by applying the parity check matrix to the second main data and the parity data; and

a sub check matrix generator configured to generate the sub parity check matrix based on a first portion of the parity check matrix by performing an exclusive OR operation on a (2i−1)-th column vector and a (2i)-th column vector adjacent to the (2i−1)-th column vector of the plurality of column vectors, i being one of 1 to k, k being a number of data bits in each of the plurality of sub data units.

10. The error correction circuit of claim 9 , wherein the syndrome decoding circuit includes:

a syndrome decoder configured to compare the syndrome to the parity check matrix and the sub parity check matrix to generate the first error decoding signal and the second error decoding signal based on a result of the comparison; and

a selection signal generator configured to generate the selection signal based on the first error decoding signal and the second error decoding signal.

11. The error correction circuit of claim 10 , wherein when the syndrome matches one of the plurality of column vectors of the parity check matrix, the syndrome decoder is configured to indicate a position of the single bit error with the first error decoding signal.

12. The error correction circuit of claim 10 , wherein when the syndrome matches one of the plurality of column vectors of the sub parity check matrix, the syndrome decoder is configured to indicate positions of the two bit errors with the second error decoding signal.

13. A semiconductor memory device, comprising:

a memory cell array including a plurality of volatile memory cells connected to word-lines and bit-lines; and

an error correction circuit configured to:

generate a parity data based on a main data and an error correction code (ECC),

store a codeword including the main data and the parity data in a target page of the memory cell array based on an access address receiving from an external device,

read the codeword from the target page,

generate a syndrome based on a parity check matrix based on the ECC, and

correct a single bit error when the single bit error exists in the main data or to correct two bit errors when the two bit errors occur in adjacent two memory cells of the target page based on the syndrome,

wherein data bits of the main data are divided into a plurality of sub data units,

wherein the ECC includes a plurality of column vectors divided into a plurality of code groups corresponding to respective ones of the plurality of sub data units,

wherein the plurality of column vectors have elements configured to gather a mis-corrected bit and multiple error bits in one symbol, and

wherein the mis-corrected bit is generated when the multiple error bits are present in the main data.

14. The semiconductor memory device of claim 13 , wherein the error correction circuit includes:

an ECC encoder configured to generate, based on a first main data obtained by selectively shifting data bits of a main data based on a least significant bit (LSB) of a row address of the access address, the parity data using the ECC; and

an ECC decoder configured to:

read the main data and the parity data from the target page,

generate the syndrome based on a second main data obtained by selectively shifting data bits of the main data based on the LSB of the row address, the parity data and the parity check matrix, and

correct the single bit error or the two bit errors based on the syndrome.

15. The semiconductor memory device of claim 14 , wherein:

the one symbol includes two adjacent sub data units of the plurality of sub data units,

the two adjacent sub data units include data bits read from two sub array regions sharing one sub word-line driver region, and

the plurality of column vectors have elements configured to place the mis-corrected bit in sub data units corresponding to the one symbol or have elements such that a column vector corresponding to the mis-corrected bit is not the same as each of the plurality of column vectors.

16. The semiconductor memory device of claim 14 , wherein the error correction circuit further includes:

a first cyclic shifter configured to generate the first main data by cyclic-shifting the data bits of the main data in a first direction in response to the LSB of the row address having a high level to provide the first main data to the ECC encoder;

a second cyclic shifter configured to generate the second main data by cyclic-shifting the data bits of the read main data in the first direction in response to the LSB of the row address having a high level to provide the second main data to the ECC decoder; and

a cyclic de-shifter configured to cyclic-shift an output data of the ECC decoder in a second direction opposite to the first direction in response to the LSB of the row address having a high level.

17. The semiconductor memory device of claim 14 , wherein:

the parity check matrix includes a plurality of column vectors divided into a plurality of code groups corresponding to the plurality of sub data units and the parity data, and

the ECC decoder is configured to generate a sub parity check matrix by performing an exclusive OR operation on a (2i−1)-th column vector and a (2i)-th column vector adjacent to the (2i−1)-th column vector of the plurality of column vectors, i being one of 1 to k, k being a number of data bits in each of the plurality of sub data units.

18. The semiconductor memory device of claim 14 , wherein the ECC decoder includes:

a syndrome generation circuit configured to generate the syndrome and a sub parity check matrix generated based on the parity check matrix, the second main data and the parity data;

a syndrome decoding circuit configured to generate a first error decoding signal associated with the single bit error, a second error decoding signal associated with the two bit errors and a selection signal by decoding the syndrome based on the parity check matrix and the sub parity check matrix;

a first corrector configured to correct the single bit error in the second main data based on the first error decoding signal to provide a first corrected data;

a second corrector configured to correct the two bit errors in the second main data based on the second error decoding signal to provide a second corrected data; and

a selection circuit configured to select one of the second main data, the first corrected data and the second corrected data in response to the selection signal to provide the selected one as an output data of the ECC decoder.

19. The semiconductor memory device of claim 13 , further comprising:

a buffer die; and

a plurality of memory dies stacked on the buffer die and configured to convey data through a plurality of through substrate via (TSV) lines,

wherein at least one of the plurality of memory dies includes the memory cell array and the error correction circuit.

20. A semiconductor memory device, comprising:

a memory cell array including a plurality of volatile memory cells connected to word-lines and bit-lines;

an error correction circuit configured to:

generate a parity data based on a main data and an error correction code (ECC),

store a codeword including the main data and the parity data in a target page of the memory cell array based on an access address receiving from an external device,

read the codeword from the target page,

generate a syndrome based on a parity check matrix based on the ECC, and

correct a single bit error when the single bit error exists in the main data or to correct two bit errors when the two bit errors occur in adjacent two memory cells in the target page based on the syndrome; and

a control logic circuit configured to control the error correction circuit based on the access address and a command receiving from the external device,

wherein the error correction circuit includes:

an ECC encoder configured to generate, based on a first main data obtained by selectively shifting data bits of the main data based on a least significant bit (LSB) of a row address of the access address, the parity data using the ECC; and

an ECC decoder configured to:

read the main data and the parity data from the target page,

generate the syndrome based on a second main data obtained by selectively shifting data bits of the main data based on the LSB of the row address, the parity data and the parity check matrix, and

correct the single bit error or the two bit errors based on the syndrome,

wherein the data bits are divided into a plurality of sub data units,

wherein the ECC includes a plurality of column vectors divided into a plurality of code groups corresponding to respective ones of the plurality of sub data units,

wherein the plurality of column vectors have elements configured to gather a mis-corrected bit and multiple error bits in one symbol, and

wherein the mis-corrected bit is generated when the multiple error bits are present in the main data.