IP Library Granted Patent US 11,552,602
Granted Patent B2
US 11,552,602 · App. 17/227,583 · Granted Jan 10, 2023

Class-D amplifier with high dynamic range

Inventors: Fong-Wen Lee (Hsinchu, TW); Wen-Chieh Wang (Hsinchu, TW); Yu-Hsin Lin (Hsinchu, TW)
Assignee: MEDIATEK INC.
H03F3/217H03K19/21H03F2200/165
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Quick Facts
Patent No.
US 11,552,602
App. No.
17/227,583
Granted
Jan 10, 2023
Kind
B2
Abstract

A class-D amplifier with good signal-to-noise ratio (SNR) performance is shown. The class-D amplifier includes a loop filter, a pulse-width modulation signal generator, a gate driver, a power driver, and a feedback circuit, which are configured to establish a closed amplification loop. The feedback circuit is configured to establish a feedback path. The class-D amplifier further includes a feedback breaker. The feedback breaker breaks the feedback path in response to conditions in which there no-signal information in the class-D amplifier.

Claims (48)

1. A class-D amplifier, comprising:

a loop filter, a pulse-width modulation signal generator, a gate driver, a power driver, and a feedback circuit, configured to establish a closed amplification loop, wherein the feedback circuit is configured to establish a feedback path; and

a feedback breaker, breaking the feedback path in response to no-signal information conditions of the class-D amplifier,

wherein:

the feedback breaker includes a logic circuit and a switch circuit;

the no-signal information conditions are detected by the logic circuit; and

when detecting the no-signal information conditions, the logic circuit outputs a switch signal to switch the switch circuit to break the feedback path.

2. The class-D amplifier as claimed in claim 1 , wherein:

an input signal of the class-D amplifier is coupled to the loop filter;

the loop filter is coupled to the pulse-width modulation signal generator;

the pulse-width modulation signal generator generates a first pulse-width modulation signal and a second pulse-width modulation signal;

the gate driver transforms the first pulse-width modulation signal and the second pulse-width modulation signal into control signals;

the power driver is controlled by the control signals to drive a load; and

the feedback circuit is coupled between the power driver and the loop filter to establish the feedback path.

3. The class-D amplifier as claimed in claim 2 , wherein:

in the no-signal information conditions, the first pulse-width modulation signal equals the second pulse-width modulation signal.

4. The class-D amplifier as claimed in claim 3 , wherein:

the logic circuit includes an Exclusive-OR gate that receives the first pulse-width modulation signal and the second pulse-width modulation signal to output the switch signal.

5. The class-D amplifier as claimed in claim 4 , wherein:

the logic circuit is combined into the gate driver.

6. The class-D amplifier as claimed in claim 4 , wherein:

the logic circuit further includes a delay unit, which delays the switch signal according to a response time of the class-D amplifier.

7. The class-D amplifier as claimed in claim 3 , which is a differential-in and differential-out amplifier, wherein:

the feedback circuit includes a first feedback resistor coupled between a positive output terminal of the class-D amplifier and a positive input terminal of the class-D amplifier, and a second feedback resistor coupled between a negative output terminal of the class-D amplifier and a negative input terminal of the class-D amplifier; and

the switch circuit includes a first switch operative to disconnect the first feedback resistor from the positive input terminal of the class-D amplifier, and a second switch operative to disconnect the second feedback resistor from the negative input terminal of the class-D amplifier.

8. The class-D amplifier as claimed in claim 7 , wherein:

the power driver includes an H-bridge circuit.

9. The class-D amplifier as claimed in claim 8 , wherein:

the logic circuit includes an Exclusive-OR gate that receives the first pulse-width modulation signal and the second pulse-width modulation signal to output the switch signal; and

the first switch and the second switch are opened by the switch signal.

10. The class-D amplifier as claimed in claim 9 , wherein:

the logic circuit is combined into the gate driver.

11. The class-D amplifier as claimed in claim 9 , wherein:

the logic circuit further includes a delay unit, which delays the switch signal according to a response time of the class-D amplifier.

12. The class-D amplifier as claimed in claim 3 , which is a single-ended in and single-ended out amplifier, wherein:

the feedback circuit includes a feedback resistor coupled between an output terminal of the class-D amplifier and an input terminal of the class-D amplifier; and

the switch circuit includes a switch operative to disconnect the feedback resistor from the input terminal of the class-D amplifier.

13. The class-D amplifier as claimed in claim 12 , wherein the power driver includes a first transistor, a second transistor, and a third transistor controlled by the gate driver, wherein:

the first transistor is coupled between a power source terminal and the output terminal of the class-D amplifier;

the second transistor is coupled between the output terminal of the class-D amplifier and a negative power source terminal; and

the third transistor is coupled between the output terminal of the class-D amplifier and a common-mode node of the class-D amplifier.

14. The class-D amplifier as claimed in claim 13 , wherein:

the logic circuit includes an Exclusive-OR gate that receives the first pulse-width modulation signal and the second pulse-width modulation signal to output the switch signal; and

the switch is opened by the switch signal.

15. The class-D amplifier as claimed in claim 14 , wherein:

the logic circuit is combined into the gate driver.

16. The class-D amplifier as claimed in claim 14 , wherein:

the logic circuit further includes a delay unit, which delays the switch signal according to a response time of the class-D amplifier.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 12, 2021
From: LEE, FONG-WEN; WANG, WEN-CHIEH; LIN, YU-HSIN
To: MEDIATEK INC.
Reel/Frame 055889/0449 →
Continuity (2)
Provisional Application 63023915 · May 13, 2020
Related Publication 20210359653A1 · Nov 18, 2021
Cited By (1)
US 12,665,551