IP Library Granted Patent US 11,960,942
Granted Patent B2
US 11,960,942 · App. 17/227,698 · Granted Apr 16, 2024

System and method for identifying lock sequence conflicts

Inventors: Ming Zhang (Beijing, CN); Lei Gao (Beijing, CN); Wai Chuen Yim (Merrimack, NH)
Assignee: EMC IP Holding Company, LLC
G06F9/524G06F16/2343
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Quick Facts
Patent No.
US 11,960,942
App. No.
17/227,698
Granted
Apr 16, 2024
Kind
B2
Abstract

A method, computer program product, and computing system for receiving a plurality of lock sequences associated with a plurality of objects of the computing device. A plurality of matrices may be generated for each lock sequence of the plurality of lock sequences, thus defining a plurality of lock sequence matrix towers. The plurality of lock sequence matrix towers may be combined, thus defining a combined lock sequence matrix tower. One or more lock sequence conflicts may be identified within the plurality of lock sequences based upon, at least in part, the combined lock sequence matrix tower.

Claims (37)

1. A computer-implemented method, executed on a computing device, comprising:

creating, using the computing device, a plurality of objects and generating a lock information binary file that includes information for each lock operation associated with the plurality of objects of the computing device;

receiving, using the computing device, a plurality of lock sequences associated with a plurality of objects of the computing device by processing the lock information binary file associated with processing the plurality of objects of the computing device at runtime;

generating, using the computing device, a matrix representative of at least a portion of a lock sequence of the plurality of lock sequences with a reference to a next matrix and an indication of a matrix tower level, wherein the matrix includes one or more rows associated with a matrix index and one or more columns associated with a lock record;

generating, using the computing device, a plurality of matrices for each lock sequence of the plurality of lock sequences to generate a lock sequence matrix tower for each lock sequence of the plurality of lock sequences for each object of the plurality of objects of the computing device;

combining, using the computing device, a plurality of lock sequence matrix towers by utilizing levels of each lock sequence matrix tower, thus defining a combined lock sequence matrix tower; and

identifying, using the computing device, one or more lock sequence conflicts within the plurality of lock sequences based upon, at least in part, the combined lock sequence matrix tower.

2. The computer-implemented method of claim 1 , wherein the matrix tower level indicates a tower level of a particular matrix in the lock sequence matrix tower.

3. The computer-implemented method of claim 1 , wherein generating the plurality of matrices for each lock sequence of the plurality of lock sequences includes generating the lock sequence matrix tower for each lock sequence based upon, at least in part, a level of one or more locks and one or more ancestor locks associated with the one or more locks.

4. The computer-implemented method of claim 1 , wherein combining the plurality of lock sequence matrix towers includes identifying a plurality of cross points in at least two lock sequence matrix towers of the plurality of lock sequence matrix towers.

5. The computer-implemented method of claim 4 , wherein combining the plurality of lock sequence matrix towers includes:

determining a sequence for the plurality of cross points in the at least two lock sequence matrix towers; and

in response to determining that the sequences for the plurality of cross points in the at least two lock sequence matrix towers are different, moving one or more locks of the plurality of cross points to a different matrix level within the combined lock sequence matrix tower.

6. The computer-implemented method of claim 5 , wherein identifying the one or more lock sequence conflicts within the plurality of lock sequences for the plurality of objects includes identifying a sequence for the plurality of cross points in the at least two lock sequence matrix towers that cannot be combined.

7. A computer program product residing on a non-transitory computer readable medium having a plurality of instructions stored thereon which, when executed by a processor, cause the processor to perform operations comprising:

creating a plurality of objects and generating a lock information binary file that includes information for each lock operation associated with the plurality of objects of the computing device;

receiving a plurality of lock sequences associated with a plurality of objects of the computing device by processing the lock information binary file associated with processing the plurality of objects of the computing device at runtime;

generating a matrix representative of at least a portion of a lock sequence of the plurality of lock sequences with a reference to a next matrix and an indication of a matrix tower level, wherein the matrix includes one or more rows associated with a matrix index and one or more columns associated with a lock record;

generating a plurality of matrices for each lock sequence of the plurality of lock sequences to generate a lock sequence matrix tower for each lock sequence of the plurality of lock sequences for each object of the plurality of objects of the computing device;

combining a plurality of lock sequence matrix towers by utilizing levels of each lock sequence matrix tower, thus defining a combined lock sequence matrix tower; and

identifying one or more lock sequence conflicts within the plurality of lock sequences based upon, at least in part, the combined lock sequence matrix tower.

8. The computer program product of claim 7 , wherein the matrix tower level indicates a tower level of a particular matrix in the lock sequence matrix tower.

9. The computer program product of claim 7 , generating the plurality of matrices for each lock sequence of the plurality of lock sequences includes generating the lock sequence matrix tower for each lock sequence based upon, at least in part, a level of one or more locks and one or more ancestor locks associated with the one or more locks.

10. The computer program product of claim 7 , wherein combining the plurality of lock sequence matrix towers includes identifying a plurality of cross points in at least two lock sequence matrix towers of the plurality of lock sequence matrix towers.

11. The computer program product of claim 10 , wherein combining the plurality of lock sequence matrix towers includes:

determining a sequence for the plurality of cross points in the at least two lock sequence matrix towers; and

in response to determining that the sequences for the plurality of cross points in the at least two lock sequence matrix towers are different, moving one or more locks of the plurality of cross points to a different matrix level within the combined lock sequence matrix tower.

12. The computer program product of claim 11 , wherein identifying the one or more lock sequence conflicts within the plurality of lock sequences for the plurality of objects includes identifying a sequence for the plurality of cross points in the at least two lock sequence matrix towers that cannot be combined.

13. A computing system comprising:

a memory; and

a processor configured to create a plurality of objects and generate a lock information binary file that includes information for each lock operation associated with the plurality of objects of the computing device, wherein the processor is further configured to receive a plurality of lock sequences associated with a plurality of objects of the computing device by processing the lock information binary file associated with processing the plurality of objects of the computing device at runtime, wherein the processor is further configured to generate a matrix representative of at least a portion of a lock sequence of the plurality of lock sequences with a reference to a next matrix and an indication of a matrix tower level, wherein the matrix includes one or more rows associated with a matrix index and one or more columns associated with a lock record, wherein the processor is further configured to generate a plurality of matrices for each lock sequence of the plurality of lock sequences to generate a lock sequence matrix tower for each lock sequence of the plurality of lock sequences for each object of the plurality of objects of the computing device, wherein the processor is further configured to combine a plurality of lock sequence matrix towers by utilizing levels of each lock sequence matrix tower, thus defining a combined lock sequence matrix tower, and wherein the processor is further configured to identify one or more lock sequence conflicts within the plurality of lock sequences based upon, at least in part, the combined lock sequence matrix tower.

14. The computing system of claim 13 , the matrix tower level indicates a tower level of a particular matrix in the lock sequence matrix tower.

15. The computing system of claim 13 , generating the plurality of matrices for each lock sequence of the plurality of lock sequences includes generating the lock sequence matrix tower for each lock sequence based upon, at least in part, a level of one or more locks and one or more ancestor locks associated with the one or more locks.

16. The computing system of claim 13 , wherein combining the plurality of lock sequence matrix towers includes identifying a plurality of cross points in at least two lock sequence matrix towers of the plurality of lock sequence matrix towers.

17. The computing system of claim 16 , wherein combining the plurality of lock sequence matrix towers includes:

determining a sequence for the plurality of cross points in the at least two lock sequence matrix towers; and

in response to determining that the sequences for the plurality of cross points in the at least two lock sequence matrix towers are different, moving one or more locks of the plurality of cross points to a different matrix level within the combined lock sequence matrix tower.

Assignments (10)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (056295/0280) Recorded Jun 10, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 062022/0255 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (056295/0124) Recorded Jun 10, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 062022/0012 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (056295/0001) Recorded Jun 10, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 062021/0844 →
RELEASE OF SECURITY INTEREST Recorded Nov 2, 2021
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 058297/0332 →
SECURITY INTEREST Recorded May 19, 2021
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 056295/0124 →
SECURITY INTEREST Recorded May 19, 2021
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 056295/0001 →
SECURITY INTEREST Recorded May 19, 2021
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 056295/0280 →
CORRECTIVE ASSIGNMENT TO CORRECT THE MISSING PATENTS THAT WERE ON THE ORIGINAL SCHEDULED SUBMITTED BUT NOT ENTERED PREVIOUSLY RECORDED AT REEL: 056250 FRAME: 0541. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 17, 2021
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
Reel/Frame 056311/0781 →
SECURITY AGREEMENT Recorded May 14, 2021
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
Reel/Frame 056250/0541 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 12, 2021
From: ZHANG, MING; GAO, LEI; YIM, WAI CHUEN
To: EMC IP HOLDING COMPANY, LLC
Reel/Frame 055890/0796 →