Method for forming an electrical contact between a semiconductor film and a bulk handle wafer, and resulting structure

1. A process, comprising:

forming an opening extending completely through a semiconductor film and an insulating layer to expose a surface of a semiconductor bulk handle wafer wherein the insulating layer is on said semiconductor bulk handle wafer and a remaining portion of the semiconductor film is on said insulating layer;

removing portions of the insulating layer under the remaining portion of the semiconductor film to form a laterally extended opening;

epitaxially baking to round said remaining portion of the semiconductor film to fill the laterally extended opening and seal an edge of the insulating layer across an entire thickness of the insulating layer;

epitaxially growing semiconductor material to fill said opening at least to a level of a top of said remaining portion of the semiconductor film; and

providing a trench isolation surrounding a region of the semiconductor film and the epitaxially grown semiconductor material in said opening to define an electrical contact made to the semiconductor bulk handle wafer that extends through said opening.

2. The process of claim 1 , further comprising:

providing a pre-metal dielectric layer on the semiconductor film; and

forming an opening extending through said pre-metal dielectric layer to support a contact made to said electrical contact.

3. The process of claim 1 , further comprising forming a heavily doped region at an upper surface of the electrical contact.

4. The process of claim 3 , further comprising siliciding at least a portion of the heavily doped region at the upper surface.

5. The process of claim 1 , wherein the trench isolation isolates the electrical contact from an active region of the semiconductor film.

6. The process of claim 5 , further comprising forming integrated circuit structures in the active region.

7. A process, comprising:

forming an opening in a silicon on insulator (SOI) substrate that extends through a semiconductor film and an insulating layer of the SOI substrate to reach a semiconductor substrate layer;

laterally extending the opening by removing portion of the insulating layer;

processing the semiconductor film at the laterally extended opening to cause the semiconductor film to seal an edge of the insulating layer across an entire thickness of the insulating layer;

epitaxially growing semiconductor material from the semiconductor substrate layer to fill said opening between portions of the semiconductor film which seal the edge of the insulating layer; and

forming a trench isolation surrounding a region of the semiconductor film which includes said portions of the semiconductor film to define an electrical contact to the semiconductor substrate layer that is made at least from the epitaxially grown semiconductor material.

8. The process of claim 7 , wherein the epitaxially grown semiconductor material has a thickness at least as thick as a thickness of the semiconductor film.

9. The process of claim 7 , wherein laterally extending the opening exposes an underside surface of the semiconductor film.

10. The process of claim 9 , wherein processing the semiconductor film comprises epitaxially processing the semiconductor film to form rounded portions at a perimeter of the opening which are in contact with the edge of the insulating layer.

11. The process of claim 7 , wherein forming the trench isolation produces an insulating structure that extends completely through the semiconductor film, and wherein the trench isolation isolates the electrical contact from an active region of the semiconductor film.

12. The process of claim 11 , further comprising forming integrated circuit structures in the active region.

13. The process of claim 7 , further comprising:

providing a pre-metal dielectric layer on the semiconductor film; and

forming an opening extending through said pre-metal dielectric layer to support a contact made to said electrical contact.

14. The process of claim 7 , further comprising forming a heavily doped region at an upper surface of the electrical contact.

15. The process of claim 14 , further comprising siliciding at least a portion of the heavily doped region at the upper surface.