IP Library Granted Patent US 11,567,892
Granted Patent B2
US 11,567,892 · App. 17/230,526 · Granted Jan 31, 2023

Bus transceiver

Inventors: Tobias Islinger (Munich, DE); Magnus-Maria Hell (Munich, DE); Maximilian Mangst (Rott am Inn, DE); Eric Pihet (Munich, DE); Jens Repp (Markt Schwaben, DE)
Assignee: Infineon Technologies AG
G06F13/4221G06F1/3253G06F13/30G06F13/382G06F13/409
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Quick Facts
Patent No.
US 11,567,892
App. No.
17/230,526
Granted
Jan 31, 2023
Kind
B2
Abstract

In accordance with an embodiment, an integrated driver circuit includes: a first connection and a second connection configured to be connected to a control chip; at least one bus connection configured to be connected to a bus line; and a control circuit. The control circuit is configured to operate in a first mode or a second mode; to output a reception signal at the second connection in the second mode, where the reception signal represents a bus signal received at the bus connection; to assume a state of low power consumption in the first mode; to change from the first mode to the second mode when a first command is detected at the first connection or at the second connection; and to change from the second mode to the first mode when the bus signal does not indicate any data for a predefined period of time.

Claims (71)

1. An integrated driver circuit having:

a first connection and a second connection configured to be connected to a control chip;

at least one bus connection configured to be connected to a bus line;

a transmitter having an output coupled to the at least one bus connection;

a receiver having an input coupled to the at least one bus connection; and

a control circuit coupled to the first connection, the second connection, the transmitter and the receiver, the control circuit configured to:

operate in a first mode or a second mode,

output a reception signal at the second connection in the second mode, wherein the reception signal represents a bus signal received at the bus connection by the receiver,

assume a state of low power consumption in the first mode,

change from the first mode to the second mode when a first command from the control chip is detected at the first connection or at the second connection,

change from the second mode to the first mode when the bus signal received by the receiver does not indicate any data for a predefined period of time,

operate in a third mode in which the transmitter is configured to transmit data received from the control chip at the first connection to the at least one bus connection, and

change from the second mode to the third mode when a second command is detected at the first connection.

2. The driver circuit as claimed in claim 1 , wherein the first command is represented by a binary signal having a particular sequence of level changes.

3. The driver circuit as claimed in claim 1 , wherein the control circuit is further configured to output a confirmation signal at the second connection after a change has been made from the second mode to the first mode after expiry of the predefined period of time.

4. The driver circuit as claimed in claim 1 , wherein:

the second connection is configured as an input in the first mode, and

the control circuit is configured to change from the first mode to the second mode when the first command is received at the second connection when the second connection is configured as an input.

5. The driver circuit as claimed in claim 4 , wherein the second connection is configured as an output in the second mode.

6. The driver circuit as claimed in claim 1 , wherein the bus signal received at the bus connection in the second mode corresponds to a 10BASE-T1S standard.

7. The driver circuit of claim 1 , wherein the receiver comprises:

a first comparator having an input coupled to the bus connection and an output coupled to the first connection; and

a second comparator having an input coupled to the bus connection and an output coupled to the second connection.

8. The driver circuit of claim 7 , wherein;

the first comparator is configured to detect bus activity on the bus connection and provide a bus activity indication signal to the first connection; and

the second comparator is configured to detect data received at the bus connection and provide the detected data to the second connection.

9. The driver circuit of claim 8 , wherein the second comparator comprises a window comparator.

10. The driver circuit of claim 7 , further comprising:

a first multiplexer having a first input coupled to the output of the first comparator, a second input coupled to a mode controller, and an output coupled to the first connection; and

a second multiplexer having a first input coupled to the output of the second comparator, a second input coupled to the mode controller, and an output coupled to the second connection.

11. The driver circuit of claim 10 , wherein the mode controller is configured to provide data to the second connection during the second mode via the second multiplexer.

12. The driver circuit of claim 10 , wherein the second comparator and the second multiplexer are configured to provide loopback data transmitted on the bus connection to the second connection during the second mode.

13. A network node comprising:

a microcontroller; and

an integrated driver circuit comprising

a first connection connected to a first pin of the microcontroller,

a second connection connected to a second pin of the microcontroller,

at least one bus connection configured to be connected to a two-wire bus line,

a transmitter having an output coupled to the at least one bus connection,

a receiver having an input coupled to the at least one bus connection, and

a control circuit coupled to the first connection, the second connection, the transmitter and the receiver, the control circuit configured to:

operate in a first mode or a second mode,

output a reception signal at the second connection in the second mode, wherein the reception signal represents a bus signal received at the bus connection by the receiver,

assume a state of low power consumption in the first mode;

change from the first mode to the second mode when a first command from the microcontroller is detected at the first connection or at the second connection,

change from the second mode to the first mode when the bus signal received by the receiver does not indicate any data for a predefined period of time, wherein the microcontroller is configured to generate the first command and transmit the first command to the driver circuit,

operate in a third mode in which the transmitter is configured to transmit data received from the microcontroller at the first connection to the at least one bus connection, and

change from the second mode to the third mode when a second command is detected at the first connection.

14. A method for operating a driver circuit, the method comprising:

receiving a first command at a first connection of the driver circuit or at a second connection of the driver circuit;

changing from a first mode to a second mode when the first command is received, wherein the driver circuit assumes a state of low power consumption in the first mode;

in the second mode, receiving a bus signal at a bus connection of the driver circuit and outputting a reception signal at the second connection of the driver circuit, wherein the reception signal represents data contained in the received bus signal;

changing from the second mode to the first mode when the bus signal does not indicate any data for a predefined period;

operating the driver circuit in a third mode comprising outputting a bus signal at the bus connection, wherein the bus signal represents a data signal received at the first connection; and

changing the driver circuit from the second mode to the third mode when a second command is detected at the first connection.

15. The method as claimed in claim 14 , further comprising outputting a confirmation signal at the second connection after a change has been made from the second mode to the first mode after expiry of the predefined period.

16. The method as claimed in claim 14 , further comprising changing from the first mode to the second mode when the first command is received at the second connection when the second connection is configured as an input.

17. The method as claimed in claim 14 , further comprising configuring the second connection as an output in the second mode.

18. The method as claimed in claim 14 , wherein receiving the bus signal at the bus connection comprises receiving the bus signal according to a 10BASE-T1S standard.

19. An integrated driver circuit having:

a first connection and a second connection configured to be connected to a control chip;

at least one bus connection configured to be connected to a bus line;

a control circuit configured to operate in a first mode or a second mode, the control circuit configured to:

output a reception signal at the second connection in the second mode, wherein the reception signal represents a bus signal received at the bus connection,

assume a state of low power consumption in the first mode,

change from the first mode to the second mode when a first command is detected at the first connection or at the second connection, and

change from the second mode to the first mode when the bus signal does not indicate any data for a predefined period of time;

a first comparator having an input coupled to the bus connection and an output coupled to the first connection;

a second comparator having an input coupled to the bus connection and an output coupled to the second connection;

a first multiplexer having a first input coupled to the output of the first comparator, a second input coupled to a mode controller, and an output coupled to the first connection; and

a second multiplexer having a first input coupled to the output of the second comparator, a second input coupled to the mode controller, and an output coupled to the second connection, wherein the mode controller is configured to provide data to the second connection during the second mode via the second multiplexer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 14, 2021
From: ISLINGER, TOBIAS; HELL, MAGNUS-MARIA; MANGST, MAXIMILIAN; PIHET, ERIC; REPP, JENS
To: INFINEON TECHNOLOGIES AG
Reel/Frame 055919/0408 →
Priority Claims (1)
DE 102020110984.9 · Apr 22, 2020 · national
Continuity (1)
Related Publication 20210334232A1 · Oct 28, 2021