System including PIPE5 to PIPE4 converter and method thereof
Embodiments of the present invention provide a PIPE5 to PIPE4 converter to provide compatibility between a PIPE5 controller and a PIPE4 test device. The converter includes a first interface coupled to the PIPE5 controller including MAC registers through a message bus interface, a second interface coupled to the PIPE4 device through a PCIe link and PHY registers. When a first message bus interface signal is received from the PIPE5 controller, the first interface finds a target PHY register based on the first message bus interface signal, and the second interface generates a first link interface signal associated with the target PHY register and outputs the first link interface signal to the PIPE4 device.
1. A system comprising:
a physical interface for a PCI express (PCIe) PIPE5 controller including a plurality of media access control (MAC) registers;
a PIPE4 device; and
a converter including a first interface coupled to the PIPE5 controller through a message bus interface, a second interface coupled to the PIPE4 device through a PCIe link and a plurality of physical (PHY) registers, wherein, when a first message bus interface signal is received from the PIPE5 controller, the first interface finds a target PHY register among the plurality of PHY registers based on the first message bus interface signal, and the second interface generates a first link interface signal associated with the target PHY register and outputs the first link interface signal to the PIPE4 device, and
wherein, when a second link interface signal is received from the PIPE4 device, the first interface finds a target MAC register among the plurality of MAC registers based on the second link interface signal and outputs a second message bus interface signal to write to the target MAC register based on the second link interface signal.
2. The system of claim 1 , wherein the first message bus interface signal and the second message bus interface signal include addresses of the target PHY and MAC registers, respectively.
3. The system of claim 1 , wherein the first link interface signal includes at least one signal which is indicated by a content of the target PHY register.
4. The system of claim 1 , wherein the first interface transmits, to the PIPE5 controller, a message bus response in response to the first message bus interface signal.
5. The system of claim 1 , wherein the second link interface signal includes data which is to be written to the target MAC register, and the second message bus interface signal includes the data and an address for the target MAC register.
6. The system of claim 1 , wherein the first interface conforms to a PIPE specification version 5.0 and the second interface conforms to a PIPE specification version 4.0.
7. The system of claim 1 , wherein the PIPE4 device includes a test device for simulation and validation.
8. A method for coupling between a PCI express (PCIe) PIPE5 controller and a PIPE4 device, the method comprising:
providing a converter including a first interface coupled to the PIPE5 controller including a plurality of media access control (MAC) registers through a message bus interface, a second interface coupled to the PIPE4 device through a PCIe link and a plurality of physical (PHY) registers;
when a first message bus interface signal is received from the PIPE5 controller, performing a first operation; and
when a second link interface signal is received from the PIPE4 device, performing a second operation,
wherein the first operation includes:
finding, by the first interface, a target PHY register among the plurality of PHY registers based on the first message bus interface signal; and
generating, by the second interface, a first link interface signal associated with the target PHY register and outputting the first link interface signal to the PIPE4 device, and
wherein the second operation includes:
finding, by the first interface, a target MAC register among the plurality of MAC registers based on the second link interface signal; and
outputting, by the first interface, a second message bus interface signal to write the target MAC register based on the second link interface signal.
9. The method of claim 8 , wherein the first message bus interface signal and the second message bus interface signal include addresses of the target PHY and MAC registers, respectively.
10. The method of claim 8 , wherein the first link interface signal includes at least one signal which is indicated by a content of the target PHY register.
11. The method of claim 8 , further comprising:
transmitting, by the first interface, to the PIPE5 controller, a message bus response in response to the first message bus interface signal.
12. The method of claim 8 , wherein the second link interface signal includes data which is to be written to the target MAC register, and the second message bus interface signal includes the data and an address for the target MAC register.
13. The method of claim 8 , wherein the first interface conforms to a PIPE specification version 5.0 and the second interface conforms to a PIPE specification version 4.0.
14. The method of claim 8 , wherein the PIPE4 device includes a test device for simulation and validation.