Method for forming semiconductor die with die region and seal-ring region
A method for forming a semiconductor die, includes forming an interlayer dielectric layer on a substrate having a semiconductor die region, a seal-ring region, and a scribe line region, forming a metal pad and a test pad on the interlayer dielectric layer, forming a passivation dielectric layer on the interlayer dielectric layer, the metal pad, and the test pad, first etching the passivation dielectric layer and the interlayer dielectric layer existing between the seal-ring region and the scribe line region to a predetermined depth using a plasma etching process, second etching the passivation dielectric layer to expose the metal pad and the test pad, forming a bump on the metal pad, and dicing the substrate while removing the scribe line region by mechanical sawing.
1. A method for forming a semiconductor die, the method comprising:
forming an interlayer dielectric layer on a substrate having a semiconductor die region, a seal-ring region, and a scribe line region;
forming a metal pad and a test pad on the interlayer dielectric layer;
forming a passivation dielectric layer on the interlayer dielectric layer, the metal pad, and the test pad;
first etching the passivation dielectric layer and the interlayer dielectric layer existing between the seal-ring region and the scribe line region to a predetermined depth using a plasma etching process;
second etching the passivation dielectric layer to expose the metal pad and the test pad;
forming a bump on the metal pad; and
dicing the substrate while removing the scribe line region by mechanical sawing.
2. The method of claim 1 , wherein the first etching exposes a surface of the substrate.
3. The method of claim 1 , wherein the first etching partially etches the interlayer dielectric layer to not expose a surface of the substrate.
4. The method of claim 3 , wherein a remaining interlayer dielectric layer has a thickness of 0.2 to 3 μm.
5. The method of claim 1 , wherein the first etching defines a conic contour in the interlayer dielectric layer.
6. The method of claim 1 , wherein the first etching etches a portion of the substrate by over-etching a surface of the substrate.
7. The method of claim 1 , wherein the interlayer dielectric layer is formed of a low-k dielectric layer.
8. A method for forming a semiconductor die, the method comprising:
forming a first interlayer dielectric layer on a substrate having a die region and a scribe line region;
forming a second interlayer dielectric layer on the first interlayer dielectric layer;
forming a metal pad in the die region and a test pad in the scribe line region, respectively, on the second interlayer dielectric layer;
forming a passivation dielectric layer on the second interlayer dielectric layer, the metal pad, and the test pad;
performing a first etching process on the passivation dielectric layer and the first and second interlayer dielectric layers formed on both sides of the test pad using a plasma etching process to expose a surface of the substrate;
performing a second etching process on the passivation dielectric layer formed on the metal pad and the test pad to expose the metal pad and the test pad;
forming a bump on the metal pad; and
dicing the substrate while removing the scribe line region using a blade dicing process.
9. The method of claim 8 , wherein the plasma etching process uses a combination of CF 4 /O 2 /N 2 gases.
10. The method of claim 8 , further comprising testing, after performing the second etching process on the passivation dielectric layer, a performance of the semiconductor device using the test pad.
11. The method of claim 8 , further comprising testing, after forming the bump on the metal pad, a connection state of the bump and the metal pad using the bump.
12. The method of claim 8 , wherein the passivation dielectric layer includes a silicon nitride layer and an oxide layer.
13. A method of forming a semiconductor device, the method comprising:
forming an interlayer dielectric layer on a substrate having a semiconductor die region and a scribe line region;
forming a metal pad in the semiconductor die region and a test pad in the scribe line region, respectively, on the interlayer dielectric layer;
forming a passivation dielectric layer on the interlayer dielectric layer, the metal pad, and the test pad; and
performing a first etching process on the passivation dielectric layer and the interlayer dielectric layer formed on both sides of the test pad to a predetermined depth using a plasma etching process;
performing a second etching process on the passivation dielectric layer formed on the metal pad and the test pad to expose the metal pad and the test pad;
forming a bump on the metal pad; and
dicing the substrate to remove the scribe line region by mechanical sawing.
14. The method of claim 13 , wherein the first etching process is performed to expose a surface of the substrate.
15. The method of claim 13 , wherein the first etching process is performed to partially etch the interlayer dielectric layer to not expose a surface of the substrate.
16. The method of claim 13 , wherein the interlayer dielectric layer comprises:
a first interlayer dielectric layer formed on the substrate;
a second interlayer dielectric layer formed on the first interlayer dielectric layer; and
a metal wire formed on the first interlayer dielectric layer.
17. The method of claim 16 , wherein the first interlayer dielectric layer is a low-k dielectric layer.
18. The method of claim 16 , wherein the first interlayer dielectric layer and the second interlayer dielectric layer are the same dielectric layer.
19. The method of claim 16 , wherein the second interlayer dielectric layer has a higher dielectric constant value than the first interlayer dielectric layer.