DDR5 crosstalk mitigation through agressor misalignment
An information handling system includes a dual in-line memory module (DIMM) and a memory controller coupled to the DIMM via a data bus. The memory controller determines that a first lane of a byte group of the data bus is more susceptible to crosstalk than a second lane of the byte group, determines a first performance level of the first lane, changes a delay (D) of a third lane of the byte group, the third lane being adjacent to the first lane, and determines that a second performance level of the first lane is different from the first performance level in response to delaying the third lane.
1. An information handling system, comprising:
a dual in-line memory module (DIMM); and
a memory controller coupled to the DIMM via a data bus, the memory controller configured to:
determine that a first lane of a byte group of the data bus is more susceptible to crosstalk than a second lane of the byte group;
determine a first performance level of the first lane;
change a delay (D) of a third lane of the byte group, the third lane being adjacent to the first lane, wherein, in changing the delay of the third lane, the memory controller is further configured to set a delay counter (N) equal to one (1), and wherein the delay (D) is given as D=N*S, where S is a preset step size of delay; and
determine that a second performance level of the first lane is different from the first performance level in response to delaying the third lane.
2. The information handling system of claim 1 , wherein, in response to determining that the second performance level is different from the first performance level, the memory controller is further configured to:
determine that the second performance level is a better performance level than the first performance level; and
change the delay (D) of the third lane of the byte group by incrementing the counter N in response to determining that the second performance level is the better performance level.
3. The information handling system of claim 2 , wherein, in further response to determining that the second performance level is different from the first performance level, the memory controller is further configured to:
determine that the second performance level is a worse performance level than the first performance level; and
change the delay (D) of the third lane of the byte group in an opposite direction such that the delay (D) is give as D=N*(−S).
4. The information handling system of claim 1 , wherein in determining that the second performance level is different from the first performance level, the memory controller is further configured to:
determine that a first signal eye of the first lane that is associated with the first performance level is different from a second signal eye of the first lane that is associated with the second performance level.
5. The information handling system of claim 1 , wherein in determining that the second performance level is different from the first performance level, the memory controller is further configured to:
determine that a first bit error rate (BER) of the first lane that is associated with the first performance level is different from a second BER of the first lane that is associated with the second performance level.
6. The information handling system of claim 5 , wherein determining the first and second BERs is based upon an alert signal from the DIMM to the memory controller.
7. The information handling system of claim 1 , further comprising:
a non-volatile memory device configured to store a ranking of the lanes of the byte group, wherein the ranking indicates a susceptibility to crosstalk for the lanes of the byte group.
8. The information handling system of claim 7 , wherein, in determining that the first lane of the byte group is more susceptible to crosstalk than the second lane of the byte group, the memory controller is further configured to:
read the ranking from the non-volatile memory device.
9. The information handling system of claim 1 , wherein the DIMM is a fifth generation double data rate (DDR5) DIMM.
10. A method, comprising:
determining, by a memory controller coupled to a dual in-line memory module (DIMM) via a data bus, that a first lane of a byte group of the data bus is more susceptible to crosstalk than a second lane of the byte group;
determining a first performance level of the first lane;
changing a delay (D) of a third lane of the byte group, the third lane being adjacent to the first lane;
setting a delay counter (N) equal to one (1), and wherein the delay (D) is given as D=N*S, where S is a preset step size of delay; and
determining that a second performance level of the first lane is different from the first performance level in response to delaying the third lane.
11. The method of claim 10 , wherein, in response to determining that the second performance level is different from the first performance level, the method further comprises:
determining that the second performance level is a better performance level than the first performance level; and
changing the delay (D) of the third lane of the byte group by incrementing the counter N in response to determining that the second performance level is the better performance level.
12. The method of claim 11 , wherein, in further response to determining that the second performance level is different from the first performance level, the method further comprises:
determining that the second performance level is a worse performance level than the first performance level; and
changing the delay (D) of the third lane of the byte group in an opposite direction such that the delay (D) is give as D=N*(−S).
13. The method of claim 10 , wherein in determining that the second performance level is different from the first performance level, the method further comprises:
determining that a first signal eye of the first lane that is associated with the first performance level is different from a second signal eye of the first lane that is associated with the second performance level.
14. The method of claim 10 , wherein in determining that the second performance level is different from the first performance level, the method further comprises:
determining that a first bit error rate (BER) of the first lane that is associated with the first performance level is different from a second BER of the first lane that is associated with the second performance level.
15. The method of claim 14 , wherein determining the first and second BERs is based upon an alert signal from the DIMM to the memory controller.
16. The method of claim 10 , further comprising:
storing, in a non-volatile memory device, a ranking of the lanes of the byte group, wherein the ranking indicates a susceptibility to crosstalk for the lanes of the byte group.
17. The method of claim 16 , wherein, in determining that the first lane of the byte group is more susceptible to crosstalk than the second lane of the byte group, the method further comprises:
reading the ranking from the non-volatile memory device.
18. An information handling system, comprising:
a fifth generation double data rate (DDR5) dual in-line memory module (DIMM); and
a DDR5 memory controller coupled to the DIMM via a data bus; and
a non-volatile memory device configured to store a ranking of lanes of a byte group of the data bus, wherein the ranking indicates a susceptibility to crosstalk for the lanes of the byte group;
wherein the DDR5 memory controller is configured to:
determine that a first lane of a byte group of the data bus is more susceptible to crosstalk than a second lane of the byte group from the ranking;
determine a first performance level of the first lane;
change a delay of a third lane of the byte group, the third lane being adjacent to the first lane, wherein, in changing the delay of the third lane, the memory controller is further configured to set a delay counter (N) equal to one (1), and wherein the delay (D) is given as D=N*S, where S is a preset step size of delay; and
determine that a second performance level of the first lane is different than the first performance level in response to delaying the third lane.