IP Library Granted Patent US 11,650,919
Granted Patent B2
US 11,650,919 · App. 17/232,428 · Granted May 16, 2023

System and method for machine learning-driven cache flushing

Inventors: Xiangping Chen (Sherborn, MA); David Meiri (Somerville, MA)
Assignee: EMC IP Holding Company, LLC
G06F12/0804G06N5/04G06N20/00G06F2212/601
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,650,919
App. No.
17/232,428
Granted
May 16, 2023
Kind
B2
Abstract

A method, computer program product, and computing system for receiving, at a cache memory system, a write request for writing data to a storage system. A data reduction rate may be predicted for the write request. One or more portions of memory within the storage system may be allocated based upon, at least in part, the predicted data reduction rate for the write request. The write request may be flushed from the cache memory system to the allocated one or more portions of memory within the storage system.

Claims (34)

1. A computer-implemented method, executed on a computing device, comprising:

receiving, at a cache memory system, a write request for writing data to a storage system;

predicting a data reduction rate for the write request;

allocating one or more portions of memory within the storage system based upon, at least in part, the predicted data reduction rate for the write request; and

flushing the write request from the cache memory system to the allocated one or more portions of memory within the storage system.

2. The computer-implemented method of claim 1 , wherein receiving the write request for writing data to the storage system includes storing the write request within the cache memory system without performing data compression or data deduplication.

3. The computer-implemented method of claim 1 , wherein predicting the data reduction rate for the write request includes training a machine learning model to predict the data reduction rate for the write request.

4. The computer-implemented method of claim 3 , wherein training the machine learning model to predict the data reduction rate for the write request includes weighting a plurality of data reduction factors for the write request.

5. The computer-implemented method of claim 1 , wherein allocating the one or more portions of memory within the storage system based upon, at least in part, the predicted data reduction rate for the write request includes allocating one or more partially utilized memory blocks within the storage system based upon, at least in part, the predicted data reduction rate for the write request.

6. The computer-implemented method of claim 1 , wherein flushing the write request from the cache memory system to the allocated one or more portions of memory within the storage system includes performing one or more data reduction operations on the write request based upon, at least in part, the predicted data reduction rate for the write request.

7. The computer-implemented method of claim 3 , further comprising:

in response to flushing the write request from the cache memory system to the allocated one or more portions of memory within the storage system, determining an actual data reduction rate for the write request; and

updating the machine learning model with the actual data reduction rate for the write request.

8. A computer program product residing on a non-transitory computer readable medium having a plurality of instructions stored thereon which, when executed by a processor, cause the processor to perform operations comprising:

receiving, at a cache memory system, a write request for writing data to a storage system;

predicting a data reduction rate for the write request;

allocating one or more portions of memory within the storage system based upon, at least in part, the predicted data reduction rate for the write request; and

flushing the write request from the cache memory system to the allocated one or more portions of memory within the storage system.

9. The computer program product of claim 8 , wherein receiving the write request for writing data to the storage system includes storing the write request within the cache memory system without performing data compression or data deduplication.

10. The computer program product of claim 8 , wherein predicting the data reduction rate for the write request includes training a machine learning model to predict the data reduction rate for the write request.

11. The computer program product of claim 10 , wherein training the machine learning model to predict the data reduction rate for the write request includes weighting a plurality of data reduction factors for the write request.

12. The computer program product of claim 8 , wherein allocating the one or more portions of memory within the storage system based upon, at least in part, the predicted data reduction rate for the write request includes allocating one or more partially utilized memory blocks within the storage system based upon, at least in part, the predicted data reduction rate for the write request.

13. The computer program product of claim 8 , wherein flushing the write request from the cache memory system to the allocated one or more portions of memory within the storage system includes performing one or more data reduction operations on the write request based upon, at least in part, the predicted data reduction rate for the write request.

14. The computer program product of claim 10 , wherein the operations further comprise:

in response to flushing the write request from the cache memory system to the allocated one or more portions of memory within the storage system, determining an actual data reduction rate for the write request; and

updating the machine learning model with the actual data reduction rate for the write request.

15. A computing system comprising:

a memory; and

a processor configured to receive, at a cache memory system, a write request for writing data to a storage system, wherein the processor is further configured to predict a data reduction rate for the write request, wherein the processor is further configured to allocate one or more portions of memory within the storage system based upon, at least in part, the predicted data reduction rate for the write request, and wherein the processor is further configured to flush the write request from the cache memory system to the allocated one or more portions of memory within the storage system.

16. The computing system of claim 15 , wherein receiving the write request for writing data to the storage system includes storing the write request within the cache memory system without performing data compression or data deduplication.

17. The computing system of claim 15 , wherein predicting the data reduction rate for the write request includes training a machine learning model to predict the data reduction rate for the write request.

18. The computing system of claim 17 , wherein training the machine learning model to predict the data reduction rate for the write request includes weighting a plurality of data reduction factors for the write request.

19. The computing system of claim 15 , wherein allocating the one or more portions of memory within the storage system based upon, at least in part, the predicted data reduction rate for the write request includes allocating one or more partially utilized memory blocks within the storage system based upon, at least in part, the predicted data reduction rate for the write request.

20. The computing system of claim 15 , wherein flushing the write request from the cache memory system to the allocated one or more portions of memory within the storage system includes performing one or more data reduction operations on the write request based upon, at least in part, the predicted data reduction rate for the write request.

Assignments (10)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (056295/0280) Recorded Jun 10, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 062022/0255 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (056295/0124) Recorded Jun 10, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 062022/0012 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (056295/0001) Recorded Jun 10, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 062021/0844 →
RELEASE OF SECURITY INTEREST Recorded Nov 2, 2021
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 058297/0332 →
SECURITY INTEREST Recorded May 19, 2021
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 056295/0124 →
SECURITY INTEREST Recorded May 19, 2021
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 056295/0001 →
SECURITY INTEREST Recorded May 19, 2021
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 056295/0280 →
CORRECTIVE ASSIGNMENT TO CORRECT THE MISSING PATENTS THAT WERE ON THE ORIGINAL SCHEDULED SUBMITTED BUT NOT ENTERED PREVIOUSLY RECORDED AT REEL: 056250 FRAME: 0541. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 17, 2021
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
Reel/Frame 056311/0781 →
SECURITY AGREEMENT Recorded May 14, 2021
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
Reel/Frame 056250/0541 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 16, 2021
From: CHEN, XIANGPING; MEIRI, DAVID
To: EMC IP HOLDING COMPANY, LLC
Reel/Frame 055941/0872 →
Continuity (1)
Related Publication 20220334966A1 · Oct 20, 2022