Mask layout, semiconductor device and manufacturing method using the same

1. A method of manufacturing a semiconductor device, the method comprising:

forming a gate insulating film on a substrate;

forming a gate electrode on the gate insulating film;

forming a source region and a drain region on both ends of the gate electrode;

forming a first insulating film on the gate electrode, the source region, and the drain region;

forming a silicide blocking film on the gate electrode, the source region, and the drain region by patterning the first insulating film; and

selectively forming a silicide film on the gate electrode disposed on an isolation region, a portion of the source region, and a portion of the drain region, such that an area where the silicide blocking film is formed on the gate electrode is greater than an area where the silicide layer is formed on the gate electrode.

2. The method of claim 1 , wherein the silicide blocking film is formed by extending from the gate electrode to the source and drain regions.

3. The method of claim 1 , wherein a gate electrode mask pattern is disposed to overlap an active mask pattern to form the gate electrode between the source region and the drain region.

4. The method of claim 3 , wherein the active mask pattern is used to form the source region and the drain region on both ends of the gate electrode.

5. The method of claim 4 , wherein a silicide blocking mask pattern is disposed to overlap the gate electrode mask pattern and the active mask pattern to form the silicide blocking film on the gate electrode, the source region, and the drain region.

6. A method of manufacturing a semiconductor device, the method comprising:

forming an active region defining an isolation region, a source region, and a drain region in a substrate;

forming a gate electrode disposed between the source region and the drain region and overlapping the active region; and

forming a gate silicide region and a silicide blocking region disposed on the gate electrode,

wherein the silicide blocking region comprises a body region and a plurality of protruding regions extended from the body region, and

wherein a horizontal width of the body region is greater than a horizontal width of each protruding region.

7. The method of claim 6 , wherein the plurality of protruding regions comprises:

a first protruding silicide blocking region disposed in the gate electrode and a portion of the source region; and

a second protruding silicide blocking region disposed in the gate electrode and a portion of the drain region.

8. The method of claim 7 , wherein the plurality of protruding regions further comprises a third protruding silicide blocking region protruded towards the drain region, and

wherein the silicide blocking region is disposed in contact with the second protruding silicide blocking region.

9. The method of claim 6 , wherein the body region is disposed to overlap the gate electrode, a portion of the source region, and a portion of the drain region.

10. The method of claim 6 , wherein the body region is disposed to overlap a portion of the gate electrode and the drain region.

11. The method of claim 10 , wherein an active mask pattern is configured to form the source region and the drain region in the substrate.

12. The method of claim 11 , wherein a gate electrode mask pattern is disposed to overlap the active mask pattern and is configured to form the gate electrode.

13. The method of claim 12 , wherein a silicide blocking mask pattern comprises a body region and protruding regions extended from the body region, and is disposed to overlap the gate electrode mask pattern and the active mask pattern to form the silicide blocking region in the gate electrode, the source region and the drain region.

14. The method of claim 13 , wherein the silicide blocking mask pattern covers the gate electrode mask pattern and extends to the active mask pattern.