IP Library Granted Patent US 11,974,442
Granted Patent B2
US 11,974,442 · App. 17/234,483 · Granted Apr 30, 2024

Semiconductor device and manufacturing method of the semiconductor device

Inventors: Hyung Keun Kim (Icheon, KR); Jun Ku Ahn (Icheon, KR); Jun Young Lim (Icheon, KR); Sung Lae Cho (Icheon, KR)
Assignee: SK hynix Inc.
H10B63/845H10B61/00H10N50/01H10N70/023H10N70/823H10B61/10H10B63/24
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Quick Facts
Patent No.
US 11,974,442
App. No.
17/234,483
Granted
Apr 30, 2024
Kind
B2
Abstract

A semiconductor device includes a stack structure including first electrodes and insulating layers alternately stacked on each other, a second electrode passing through the stack structure, and variable resistance patterns each interposed between the second electrode and a corresponding one of the first electrodes. Each of the first electrodes includes a first sidewall facing the second electrode, and each of the insulating layers includes a second sidewall facing the second electrode. At least a part of each of the variable resistance patterns protrudes farther towards the second electrode than the second sidewall.

Claims (30)

1. A method of manufacturing a semiconductor device, the method comprising:

forming a stack structure including first material layers and second material layers alternately stacked on each other;

forming a first opening passing through the stack structure;

forming variable resistance patterns by selectively forming a variable resistance material on sidewalls of the first material layers, the variable resistance patterns protruding beyond the second material layers and extending into the first opening, wherein the variable resistance patterns include first portions grown from the first material layers in a first direction and second portions grown from the first portions in a second direction, and the second portions arranged in the second direction are spaced apart from each other; and

forming a first electrode in the first opening,

wherein forming the variable resistance patterns comprises selectively growing the variable resistance material by using the first material layers that are exposed through the first opening as seeds.

2. The method of claim 1 , further comprising:

forming second openings coupled to the first opening, each of the second openings being located between an adjacent pair of the second material layers.

3. The method of claim 2 , wherein the first portions are grown in the second openings, the second portions are grown from the first portions in the first opening, and each of the second portions extends beyond a corresponding one of the first portions in the second direction.

4. The method of claim 3 , wherein the second material layers have sidewalls facing the first opening, and

wherein the second portion includes a curved surface that covers a portion of the sidewalls facing the first opening.

5. The method of claim 2 , further comprising:

forming a sacrificial layer in the first opening and the second openings;

replacing the first material layers with third material layers so that the variable resistance material is formed on sidewalls of the third material layers; and

removing the sacrificial layer.

6. The method of claim 2 , wherein the second openings are formed by selectively etching the first material layers through the first opening, the second openings each extending in a direction that is substantially orthogonal to the first opening.

7. The method of claim 1 , further comprising:

forming a sacrificial layer in the first opening;

replacing the first material layers with third material layers so that the variable resistance material is formed on sidewalls of the third material layers; and

forming second openings by selectively etching the third material layers through the first opening.

8. The method of claim 1 , wherein the variable resistance patterns are spaced apart from each other in the second direction in which the first material layers and the second material layers are stacked.

9. The method of claim 1 , wherein each of the variable resistance patterns includes a chalcogenide that maintains an amorphous state when a program operation is performed.

10. A method of manufacturing a semiconductor device, the method comprising:

forming a stack structure including first material layers and second material layers alternately stacked on each other;

forming a first opening passing through the stack structure;

forming variable resistance patterns by selectively forming a variable resistance material on sidewalls of the first material layers, the variable resistance patterns protruding beyond the second material layers and extending into the first opening, wherein the variable resistance patterns include first portions grown from the first material layers in a first direction and second portions grown from the first portions in a second direction, and the second portions arranged in the second direction are spaced apart from each other;

forming a first electrode in the first opening;

forming a sacrificial layer in the first opening;

replacing the first material layers with third material layers so that the variable resistance material is formed on sidewalls of the third material layers; and

forming second openings by selectively etching the third material layers through the first opening.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 20, 2021
From: KIM, HYUNG KEUN; AHN, JUN KU; LIM, JUN YOUNG; CHO, SUNG LAE
To: SK HYNIX INC.
Reel/Frame 055976/0067 →
Priority Claims (1)
KR 10-2020-0158217 · Nov 23, 2020 · national
Continuity (1)
Related Publication 20220165791A1 · May 26, 2022