Memory arrays comprising vertically-alternating tiers of insulative material and memory cells and methods of forming a memory array comprising memory cells individually comprising a transistor and a capacitor

1. A memory array comprising vertically-alternating tiers of insulative material and memory cells, the memory cells individually comprising:

 a transistor comprising first and second source/drain regions having a channel region there-between, at least a portion of the channel region being horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions; and

 a capacitor comprising first and second electrodes having a capacitor insulator there-between, the first electrode being electrically coupled to the first source/drain region, the second capacitor electrodes of multiple of the capacitors in the array being electrically coupled with one another;

a pair of laterally-spaced access-line pillars extending elevationally through the vertically-alternating tiers on opposite sides of individual ones of the channel regions that are in different ones of the memory-cell tiers, portions of the access-line pillars in the different memory-cell tiers comprising a pair of gates on the opposite sides of the individual channel regions of individual ones of the transistors in the different memory-cell tiers;

a sense line electrically coupled to individual ones of multiple of the second source/drain regions;

the individual transistors comprising a gate insulator that is laterally between the gate and the channel region, the gate insulator being laterally between and separating the gate and the first source/drain region from physically contacting one another, the gate insulator being laterally between and separating the gate and the second source/drain region from physically contacting one another; and

the first and second source/drain regions each have a vertical side that is directly against both of the channel region and the gate insulator, a greater quantity of each of the vertical sides of the first and second source/drain regions being directly against the gate insulator than is directly against the channel region.

2. The array of claim 1 comprising a horizontally-extending conductive strap that directly electrically couples the pair of access-line pillars together.

3. The array of claim 2 comprising a horizontal longitudinally-elongated conductive line directly electrically coupled to the conductive strap of multiple of the pairs of access-line pillars.

4. The array of claim 2 wherein the conductive strap is above the pair of access-line pillars.

5. The array of claim 4 comprising a horizontal longitudinally-elongated conductive line directly electrically coupled to the conductive strap of multiple of the pairs of access-line pillars.

6. A memory array comprising vertically-alternating tiers of insulative material and memory cells, the memory cells individually comprising:

 a transistor comprising first and second source/drain regions having a channel region there-between, at least a portion of the channel region being horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions; and

 a capacitor comprising first and second electrodes having a capacitor insulator there-between, the first electrode being electrically coupled to the first source/drain region, the second capacitor electrodes of multiple of the capacitors in the array being electrically coupled with one another;

a pair of laterally-spaced access-line pillars extending elevationally through the vertically-alternating tiers on opposite sides of individual ones of the channel regions that are in different ones of the memory-cell tiers, portions of the access-line pillars in the different memory-cell tiers comprising a pair of gates on the opposite sides of the individual channel regions of individual ones of the transistors in the different memory-cell tiers;

a sense line electrically coupled to individual ones of multiple of the second source/drain regions along a y-direction;

a conductive strap that is longitudinally-elongated along the y-direction, the conductive strap directly electrically coupling the pair of access-line pillars together; and

two conductive lines that are longitudinally-elongated along an x-direction that is orthogonal to the y-direction, one of the two conductive lines directly electrically coupling together a first series of the conductive straps of multiple of the pairs of access-line pillars that alternate relative to one another along the x-direction, the other of the two conductive lines directly electrically coupling together a second series of the conductive straps of multiple of the pairs of access-line pillars that alternate relative to one another and to the first series of the conductive straps along the x-direction.

7. A memory array comprising vertically-alternating tiers of insulative material and memory cells, the memory cells individually comprising:

 a transistor comprising first and second source/drain regions having a channel region there-between, at least a portion of the channel region being horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions; and

 a capacitor comprising first and second electrodes having a capacitor insulator there-between, the first electrode being electrically coupled to the first source/drain region, the second capacitor electrodes of multiple of the capacitors in the array being electrically coupled with one another;

a pair of laterally-spaced access-line pillars extending elevationally through the vertically-alternating tiers on opposite sides of individual ones of the channel regions that are in different ones of the memory-cell tiers, portions of the access-line pillars in the different memory-cell tiers comprising a pair of gates on the opposite sides of the individual channel regions of individual ones of the transistors in the different memory-cell tiers;

a sense line electrically coupled to individual ones of multiple of the second source/drain regions;

a conductive strap above the pair of access-line pillars that is longitudinally-elongated and directly electrically couples the pair of access-line pillars together;

a conductive line above the conductive strap that is longitudinally-elongated along an x-direction and that directly electrically couples to the conductive strap of multiple of the pairs of access-line pillars; and

a conductive line below the conductive line that is above the conductive strap and that is longitudinally-elongated along a y-direction that is orthogonal to the x-direction, the conductive line that is longitudinally-elongated in the y-direction directly electrically coupling together individual ones of the second capacitor electrodes.