Granted Patent B2

US 11,941,253 · App. 17/237,560 · Granted Mar 26, 2024

Inventors: Oran Baruch (Tel Aviv, IL); Ronen Gazit (Tel Aviv, IL); Jenny Derzhavetz (Ra'anana, IL)

Assignee: EMC IP Holding Company, LLC

G06F3/0619G06F3/0653G06F3/0673

Abstract

Claims (77)

1. A computer-implemented method, executed on a computing device, comprising:

sensing a failure within a system within a computing device, wherein the system includes a cache memory system and a vaulted memory comprising a random access memory (RAM) having a plurality of independent persistent areas;

providing a primary node and a secondary node, wherein the primary node occupies a first independent persistent area of the RAM of the vaulted memory and the secondary node occupies a second independent persistent area of the RAM of the vaulted memory; and

writing data within the vaulted memory to a persistent media using an iterator, wherein the data includes at least one dirty page, and

wherein writing data within the vaulted memory to the persistent media using the iterator includes:

flushing the at least one dirty page to the persistent media;

determining whether at least one of the plurality of components within the vaulted memory includes a bitmap;

in response to determining the at least one of the plurality of components within the vaulted memory includes the bitmap, determining if the bitmap is associated with a dirty page; and

iterating, in response to determining the bitmap is associated with the dirty page, the dirty page, wherein iterating the dirty page includes returning a size and an address of the bitmap to the vaulted memory.

2. The computer-implemented method of claim 1 , further comprising:

receiving an initial address and size of the vaulted memory; and

partitioning a plurality of components within the vaulted memory based upon, at least in part, the received initial address and size of the vaulted memory.

3. The computer-implemented method of claim 1 , wherein writing data within the vaulted memory to a persistent media using an iterator further includes:

determining at least one of the plurality of components does not include a bitmap; and

returning a size and address of the at least one component of the plurality of components to a beginning portion of the at least one component of the plurality of components.

4. The computer-implemented method of claim 1 , further comprising:

identifying the primary node as an initiator node, wherein the initiator node receives a commit request via the primary node, wherein the commit request includes a request to commit data within the vaulted memory to the persistent media;

transferring, via the primary node, a dirty bitmap and a page descriptor to a secondary node;

processing, in response to transferring the dirty bitmap and page descriptor via the secondary node, the dirty bitmap and page descriptor, wherein processing the dirty bitmap and page descriptor includes removing the page descriptor, allocating a new page descriptor, logging the new page descriptor, and updating a cache of the cache memory system;

sending an update, in response to processing the dirty bitmap and page descriptor, to the primary node via the secondary node, wherein the update includes the new page descriptor; and

logging the update with the new page descriptor in the primary node.

5. The computer-implemented method of claim 1 , further comprising:

identifying the secondary node as an initiator node, wherein the initiator node receives a commit request via the secondary node, wherein the commit request includes a request to commit data within the vaulted memory to the persistent media;

transferring, via a secondary node, a dirty bitmap and a page descriptor to the primary node; processing, in response to transferring the dirty bitmap and page descriptor via the primary node, the dirty bitmap and page descriptor, wherein processing the dirty bitmap and page descriptor includes removing the page descriptor, allocating a new page descriptor, logging the new page descriptor with a data offset, wherein the data offset is an index of a remote node, and updating a cache of the cache memory system;

sending an update, in response to processing the dirty bitmap and page descriptor, to the secondary node via the primary node, wherein the update includes the new page descriptor; and

logging the update with the new page descriptor in the secondary node.

6. The computer-implemented method of claim 1 , wherein writing data within the vaulted memory to a persistent media using an iterator does not require use of non-volatile random access memory (NVRAM) that utilizes a data journal.

7. A computer program product residing on a non-transitory computer readable medium having a plurality of instructions stored thereon which, when executed by a processor, cause the processor to perform operations comprising:

sensing a failure within a system within a computing device, wherein the system includes a cache memory system and a vaulted memory comprising a random access memory (RAM) having a plurality of independent persistent areas;

providing a primary node and a secondary node, wherein the primary node occupies a first independent persistent area of the RAM of the vaulted memory and the secondary node occupies a second independent persistent area of the RAM of the vaulted memory; and

writing data within the vaulted memory to a persistent media using an iterator, wherein the data includes at least one dirty page, and

wherein writing data within the vaulted memory to the persistent media using the iterator includes:

flushing the at least one dirty page to the persistent media;

determining whether at least one of the plurality of components within the vaulted memory includes a bitmap;

in response to determining the at least one of the plurality of components within the vaulted memory includes the bitmap, determining if the bitmap is associated with a dirty page; and

iterating, in response to determining the bitmap is associated with the dirty page, the dirty page, wherein iterating the dirty page includes returning a size and an address of the bitmap to the vaulted memory.

8. The computer program product of claim 7 , further comprising:

receiving an initial address and size of the vaulted memory; and

partitioning a plurality of components within the vaulted memory based upon, at least in part, the received initial address and size of the vaulted memory.

9. The computer program product of claim 7 , wherein writing data within the vaulted memory to a persistent media using an iterator further includes:

determining at least one of the plurality of components does not include a bitmap; and

returning a size and address of the at least one component of the plurality of components to a beginning portion of the at least one component of the plurality of components.

10. The computer program product of claim 7 , further comprising:

identifying the primary node as an initiator node, wherein the initiator node receives a commit request via the primary node, wherein the commit request includes a request to commit data within the vaulted memory to the persistent media; transferring, via the primary node, a dirty bitmap and a page descriptor to a secondary node;

processing, in response to transferring the dirty bitmap and page descriptor via the secondary node, the dirty bitmap and page descriptor, wherein processing the dirty bitmap and page descriptor includes removing the page descriptor, allocating a new page descriptor, logging the new page descriptor, and updating a cache of the cache memory system;

sending an update, in response to processing the dirty bitmap and page descriptor, to the primary node via the secondary node, wherein the update includes the new page descriptor; and

logging the update with the new page descriptor in the primary node.

11. The computer program product of claim 7 , further comprising:

identifying the secondary node as an initiator node, wherein the initiator node receives a commit request via the secondary node, wherein the commit request includes a request to commit data within the vaulted memory to the persistent media; transferring, via a secondary node, a dirty bitmap and a page descriptor to the primary node;

processing, in response to transferring the dirty bitmap and page descriptor via the primary node, the dirty bitmap and page descriptor, wherein processing the dirty bitmap and page descriptor includes removing the page descriptor, allocating a new page descriptor, logging the new page descriptor with a data offset, wherein the data offset is an index of a remote node, and updating a cache of the cache memory system;

sending an update, in response to processing the dirty bitmap and page descriptor, to the secondary node via the primary node, wherein the update includes the new page descriptor; and

logging the update with the new page descriptor in the secondary node.

12. The computer program product of claim 7 , wherein writing data within the vaulted memory to a persistent media using an iterator does not require use of non-volatile random access memory (NVRAM) that utilizes a data journal.

13. A computing system comprising:

a memory; and

a processor configured to sense a failure within a system within a computing device, wherein the system includes a cache memory system and a vaulted memory comprising a random access memory (RAM) having a plurality of independent persistent areas, wherein the processor is further configured to provide a primary node and a secondary node, wherein the primary node occupies a first independent persistent area of the RAM of the vaulted memory and the secondary node occupies a second independent persistent area of the RAM of the vaulted memory, and wherein the processor is further configured to write data within the vaulted memory to a persistent media using an iterator, wherein the data includes at least one dirty page, and wherein writing data within the vaulted memory to the persistent media using the iterator includes:

flushing the at least one dirty page to the persistent media,

determining whether at least one of the plurality of components within the vaulted memory includes a bitmap,

in response to determining the at least one of the plurality of components within the vaulted memory includes the bitmap, determining if the bitmap is associated with a dirty page, and

iterating, in response to determining the bitmap is associated with the dirty page, the dirty page, wherein iterating the dirty page includes returning a size and an address of the bitmap to the vaulted memory.

14. The computing system of claim 13 , wherein the process is further configured to:

receive an initial address and size of the vaulted memory; and

partition a plurality of components within the vaulted memory based upon, at least in part, the received initial address and size of the vaulted memory.

15. The computing system of claim 13 , wherein writing data within the vaulted memory to a persistent media using an iterator further includes:

determining at least one of the plurality of components does not include a bitmap; and

returning a size and address of the at least one component of the plurality of components to a beginning portion of the at least one component of the plurality of components.

16. The computing system of claim 13 , wherein the processor is further configured to:

identify the primary node as an initiator node, wherein the initiator node receives a commit request via the primary node, wherein the commit request includes a request to commit data within the vaulted memory to the persistent media;

transfer, via the primary node, a dirty bitmap and a page descriptor to a secondary node; process, in response to transferring the dirty bitmap and page descriptor via the secondary node, the dirty bitmap and page descriptor, wherein processing the dirty bitmap and page descriptor includes removing the page descriptor, allocating a new page descriptor, logging the new page descriptor, and updating a cache of the cache memory system;

send an update, in response to processing the dirty bitmap and page descriptor, to the primary node via the secondary node, wherein the update includes the new page descriptor; and

log the update with the new page descriptor in the primary node.

17. The computing system of claim 13 , wherein the processor is further configured to:

identify the secondary node as an initiator node, wherein the initiator node receives a commit request via the secondary node, wherein the commit request includes a request to commit data within the vaulted memory to the persistent media;

transfer, via a secondary node, a dirty bitmap and a page descriptor to the primary node; process, in response to transferring the dirty bitmap and page descriptor via the primary node, the dirty bitmap and page descriptor, wherein processing the dirty bitmap and page descriptor includes removing the page descriptor, allocating a new page descriptor, logging the new page descriptor with a data offset, wherein the data offset is an index of a remote node, and updating a cache of the cache memory system;

send an update, in response to processing the dirty bitmap and page descriptor, to the secondary node via the primary node, wherein the update includes the new page descriptor; and

log the update with the new page descriptor in the secondary node.

18. The computing system of claim 13 , wherein writing data within the vaulted memory to a persistent media using an iterator does not require use of non-volatile random access memory (NVRAM) that utilizes a data journal.

Assignments (10)

Continuity (1)