Display panel and display apparatus including the same

1. A display panel, comprising:

a display region and a non-display region surrounding the display region,

wherein the non-display region comprises a step region, a left border and a right border that are adjacent to the step region, and an upper border arranged opposite to the step region, and wherein the left border, the right border, the upper border, and the step region surround the display region;

wherein the left border and the right border each comprise an encapsulation region;

wherein the encapsulation region comprises a sealant and a reflective metal layer that are at least partially overlapped with each other; and

wherein the step region comprises a ground metal line, and wherein the ground metal line is connected to the reflective metal layer through an electrostatic consumption resistance portion,

wherein the display panel further comprises:

a substrate, an active layer, a gate insulation layer, a gate metal layer, an interlayer insulation layer, a source-drain metal layer, a planarization layer, a first electrode layer, a pixel definition layer, an organic light-emitting layer, and a second electrode layer that are sequentially stacked; and

a scan signal line located in the gate metal layer and a data signal line located in the source-drain metal layer; wherein the scan signal line intersects with the data signal line,

wherein the electrostatic consumption resistance portion comprises a first electrostatic consumption resistance portion located at the gate metal layer.

2. The display panel according to claim 1 ,

wherein the source-drain metal layer has a smaller sheet resistance than that of the gate metal layer.

3. The display panel according to claim 1 , wherein the electrostatic consumption resistance portion comprises a disconnection portion.

4. The display panel according to claim 1 , wherein the electrostatic consumption resistance portion comprises a second electrostatic consumption resistance portion located in the active layer, and wherein the second electrostatic consumption resistance portion has a smaller doping concentration than a lightly doped region of the active layer.

5. The display panel according to claim 1 , wherein the electrostatic consumption resistance portion comprises:

an active layer portion and a gate portion, wherein the active layer portion is located in the active layer and has a smaller doping concentration than a lightly doped region of the active layer;

and wherein the gate portion at least partially overlaps with the active layer portion, wherein the gate portion and the active layer portion constitute an electrostatic consumption resistance transistor, and wherein a first voltage, when applied to the gate portion, cuts off the electrostatic consumption resistance transistor.

6. The display panel according to claim 1 , wherein a plurality of sections of the electrostatic consumption resistance portions is arranged in series.

7. The display panel according to claim 6 , wherein:

a plurality of sections of the disconnection portions is arranged in series; or, a plurality of sections of the first electrostatic consumption resistance portions is arranged in series; or, a plurality of sections of the second electrostatic consumption resistance portions is arranged in series; or, a plurality of sections of the electrostatic consumption resistance transistors is arranged in series.

8. The display panel according to claim 6 , wherein the plurality of sections of the electrostatic consumption resistance portion arranged in series comprises at least two of the disconnection portion, the first electrostatic consumption resistance portion, the second electrostatic consumption resistance portion, and the electrostatic consumption resistance transistor.

9. The display panel according to claim 8 , wherein:

the first electrostatic consumption resistance portion is away from the reflective metal layer and close to the ground metal line when the plurality of sections of the electrostatic consumption resistance portion connected in series comprises the first electrostatic consumption resistance portion.

10. A display panel, comprising:

a display region and a non-display region surrounding the display region,

wherein the non-display region comprises a step region, a left border and a right border that are adjacent to the step region, and an upper border arranged opposite to the step region, and wherein the left border, the right border, the upper border, and the step region surround the display region;

wherein the left border and the right border each comprise an encapsulation region;

wherein the encapsulation region comprises a sealant and a reflective metal layer that are at least partially overlapped with each other; and

wherein the step region comprises a ground metal line, and wherein the ground metal line is connected to the reflective metal layer through an electrostatic consumption resistance portion,

wherein the display panel further comprises a binding terminal and a test circuit which are electrically connected through a connection line;

wherein the test circuit is configured to short-circuit the data signal line during test;

wherein the connection line at least partially overlaps with the ground metal line; and

wherein the connection line comprises a first connection line overlapping with the ground metal line, and wherein the ground metal line comprises a first ground metal line overlapping with the connection line.

11. The display panel according to claim 10 , wherein:

the connection line comprises an overlapping portion overlapping with the ground metal line and a non-overlapping portion that does not overlap with the ground metal line, the overlapping portion having a greater width than the non-overlapping portion.

12. The display panel according to claim 10 , further comprising:

an electro-static discharge protection device electrically connected to the connection line, wherein the electro-static discharge protection device comprises a first diode and a second diode;

wherein a positive electrode of the first diode is connected to the connection line, and a negative electrode of the first diode is connected to a high-level signal line; and

wherein a negative electrode of the second diode is connected to the connection line, and a positive electrode of the second diode is connected to a low-level signal line.

13. The display panel according to claim 10 wherein:

the first connection line is located in the active layer and has a doping concentration greater than or equal to a doping concentration of a heavily doped region;

and wherein at least the gate insulation layer, a first interlayer insulation layer and a second interlayer insulation layer are arranged in a direction perpendicular to the display panel.

14. The display panel according to claim 13 , wherein:

the first ground metal line is located in the first electrode layer;

and wherein at least the gate insulation layer, the first interlayer insulation layer, the second interlayer insulation layer, and the planarization layer are arranged between the first connection line and the first ground metal line in the direction perpendicular to the display panel.

15. The display panel according to claim 10 , wherein:

at least two inorganic insulation layers and one organic insulation layer are arranged between the first ground metal line and the first connection line, and a distance between the first ground metal line and the first connection line is greater than or equal to 1.8 μm in a direction perpendicular to the display panel.

16. A display apparatus, comprising a display panel, wherein the display panel comprises:

a display region and a non-display region surrounding the display region,

wherein the non-display region comprises a step region, a left border and a right border that are adjacent to the step region, and an upper border arranged opposite to the step region;

wherein the left border, the right border, the upper border, and the step region surround the display region;

wherein the left border and the right border each comprise an encapsulation region;

wherein the encapsulation region comprises a sealant and a reflective metal layer that are at least partially overlapped with each other; and

wherein the step region comprises a ground metal line, and the ground metal line is connected to the reflective metal layer through an electrostatic consumption resistance portion,

wherein the display panel further comprises:

a substrate, an active layer, a gate insulation layer, a gate metal layer, an interlayer insulation layer, a source-drain metal layer, a planarization layer, a first electrode layer, a pixel definition layer, an organic light-emitting layer, and a second electrode layer that are sequentially stacked; and

a scan signal line located in the gate metal layer and a data signal line located in the source-drain metal layer; wherein the scan signal line intersects with the data signal line,

wherein the electrostatic consumption resistance portion comprises a first electrostatic consumption resistance portion located at the gate metal layer.

17. The display apparatus according to claim 16 ,

wherein the source-drain metal layer has a smaller sheet resistance than the gate metal layer.

18. The display apparatus according to claim 16 , wherein the electrostatic consumption resistance portion comprises a second electrostatic consumption resistance portion located in the active layer, and wherein the second electrostatic consumption resistance portion has a smaller doping concentration than a lightly doped region of the active layer.

19. The display apparatus according to claim 16 , wherein:

the electrostatic consumption resistance portion comprises an active layer portion and a gate portion, wherein the active layer portion is located in the active layer and has a smaller doping concentration than a lightly doped region of the active layer;

wherein the gate portion at least partially overlaps with the active layer portion, wherein the gate portion and the active layer portion constitute an electrostatic consumption resistance transistor, and wherein the gate portion is applied with a first voltage to cut off the electrostatic consumption resistance transistor.

20. The display apparatus according to claim 16 , wherein the display panel further comprises a binding terminal and a test circuit which are electrically connected through a connection line;

wherein the test circuit is configured to short-circuit the data signal line during test;

wherein the connection line at least partially overlaps with the ground metal line; and

wherein the connection line comprises a first connection line overlapping with the ground metal line, and wherein the ground metal line comprises a first ground metal line overlapping with the connection line.