Electronic circuit having vertical hall elements arranged on a substrate to reduce an orthogonality error
An electronic circuit can have a first plurality of vertical Hall elements and a second plurality of vertical Hall elements all disposed on a substrate having a plurality of crystal unit cells, wherein the first plurality of vertical Hall elements have longitudinal axes disposed within five degrees of parallel to an edge of the crystal unit cells, and wherein the second plurality of vertical Hall elements have longitudinal axes disposed between eighty-five and ninety-five degrees relative to the longitudinal axes of the first plurality of vertical Hall elements.
1. An electronic circuit, comprising:
a substrate having a major surface, the substrate comprising a plurality of unit crystal cells, the plurality of unit crystal cells having a crystal axis parallel to an edge of one of the plurality of unit crystal cells and parallel to the major surface of the substrate;
a first plurality of vertical Hall elements coupled in a first parallel arrangement, each one of the first plurality of vertical Hall elements having a respective longest dimension and a respective shortest dimension parallel to a first axis, the first axis parallel to the major surface of the substrate, wherein the first axis is disposed in a direction of between plus five and minus five degrees relative to the crystal axis, wherein the first plurality of vertical Hall elements taken together has a first geometric centroid on the major surface of the substrate; and
a second plurality of vertical Hall elements coupled in a second parallel arrangement, each one of the second plurality of vertical Hall elements having a respective longest dimension and a respective shortest dimension parallel to a second axis, the second axis parallel to the major surface of the substrate, wherein an angle between the first and second axes is between eighty-five and ninety-five degrees, wherein the second plurality of vertical Hall elements taken together has a second geometric centroid on the major surface of the substrate, wherein the first and second centroids have a separation on the major surface of the substrate less than half of the longest dimension plus two times the shortest dimension of any one of the first plurality or the second plurality of vertical Hall elements.
2. The electronic circuit of claim 1 , wherein the first plurality of vertical Hall elements comprises a first two vertical Hall elements and the second plurality of vertical Hall elements comprises a second two vertical Hall elements.
3. The electronic circuit of claim 1 , wherein the first plurality of vertical Hall elements comprises a first four vertical Hall elements and the second plurality of vertical Hall elements comprises a second four vertical Hall elements.
4. The electronic circuit of claim 1 , wherein the first and second centroids are at a same point on the major surface of the substrate.
5. The electronic circuit of claim 4 , wherein the first plurality of vertical Hall elements comprises a first four vertical Hall elements and the second plurality of vertical Hall elements comprises a second four vertical Hall elements.
6. The electronic circuit of claim 1 , wherein the first and second pluralities of vertical Hall elements are disposed in an interdigitated arrangement such that ones of the first plurality of vertical Hall elements are disposed between ones of the second plurality of vertical Hall elements.
7. The electronic circuit of claim 6 , wherein the first plurality of vertical Hall elements comprises a first four vertical Hall elements and the second plurality of vertical Hall elements comprises a second four vertical Hall elements.
8. The electronic circuit of claim 1 , further comprising:
a planar Hall element disposed on the major surface of the substrate, wherein the planar Hall element has a third geometric centroid.
9. The electronic circuit of claim 8 , wherein the first plurality of vertical Hall elements and the second plurality of vertical Hall elements are proximate to and surround the planar Hall element, and wherein the first, second, and third centroids are at a same point on the major surface of the substrate.
10. The electronic circuit of claim 9 , wherein the first plurality of vertical Hall elements comprises a first four vertical Hall elements and the second plurality of vertical Hall elements comprises a second four vertical Hall elements.
11. The electronic circuit of claim 8 , wherein the first plurality of vertical Hall elements and the second plurality of vertical Hall elements surround the planar Hall element, wherein the first and second pluralities of vertical Hall elements are disposed in an interdigitated arrangement such that ones of the first plurality of vertical Hall elements are disposed between ones of the second plurality of vertical Hall elements.
12. The electronic circuit of claim 11 , wherein the first plurality of vertical Hall elements comprises a first four vertical Hall elements and the second plurality of vertical Hall elements comprises a second four vertical Hall elements.
13. The electronic circuit of claim 1 , further comprising:
a plurality of planar Hall elements coupled in parallel and disposed on the major surface of the substrate, wherein the plurality of planar Hall element taken together has a third geometric centroid.
14. The electronic circuit of claim 13 , wherein the plurality of planar Hall elements comprises four planar Hall elements.
15. The electronic circuit of claim 14 , wherein the first plurality of vertical Hall elements comprises a first four vertical Hall elements and the second plurality of vertical Hall elements comprises a second four vertical Hall elements.
16. The electronic circuit of claim 15 , wherein the first, second, and third centroids are at a same point on the major surface of the substrate.
17. The electronic circuit of claim 16 , wherein the first plurality of vertical Hall elements and the second plurality of vertical Hall elements are disposed between ones of the plurality of planar Hall elements.
18. The electronic circuit of claim 16 , wherein each one of the first plurality of vertical Hall elements is electrically coupled in a different respective phase at any particular time, and wherein each one of the second plurality of vertical Hall element is electrically coupled in a different respective phase at any particular time.
19. The electronic circuit of claim 18 , wherein each one of the plurality of planar Hall elements is electrically coupled in a different respective phase at any particular time.
20. The electronic circuit of claim 18 , wherein the first plurality of vertical Hall elements and the second plurality of vertical Hall elements are disposed between ones of the plurality of planar Hall elements.
21. The electronic circuit of claim 15 , wherein the first and second pluralities of vertical Hall elements are disposed in an interdigitated arrangement such that ones of the first plurality of vertical Hall elements are disposed between ones of the second plurality of vertical Hall elements.
22. The electronic circuit of claim 21 , wherein each one of the first plurality of vertical Hall elements is electrically coupled in a different respective phase at any particular time, and wherein each one of the second plurality of vertical Hall element is electrically coupled in a different respective phase at any particular time.
23. The electronic circuit of claim 22 , wherein each one of the plurality of planar Hall elements is electrically coupled in a different respective phase at any particular time.
24. The electronic circuit of claim 15 , wherein each one of the first plurality of vertical Hall elements is electrically coupled in a different respective phase at any particular time, and wherein each one of the second plurality of vertical Hall element is electrically coupled in a different respective phase at any particular time.
25. The electronic circuit of claim 24 , wherein each one of the plurality of planar Hall elements is electrically coupled in a different respective phase at any particular time.
26. The electronic circuit of claim 1 , wherein each separation between each respective center of each one of the first plurality of vertical Hall elements and other ones of the centers of the first plurality of vertical Hall elements is greater than half the longest dimension of any one of the first plurality of vertical Hall elements and wherein each separation between each respective center of each one of the second plurality of vertical Hall elements and other ones of the centers of the second plurality of vertical Hall elements is greater than half the longest dimension of any one of the second plurality of vertical Hall elements.