Switch pruning in a switch fabric bus chassis
Bus enumeration of a switch fabric bus may be performed without assigning bus numbers to unused switch ports and/or corresponding slots to which the unused switch ports are routed. Accordingly, switches coupled to a switch fabric bus in a chassis may link-train with corresponding slots in the chassis in an attempt to establish active connections with devices coupled to the slots. Unused switch fabric bus lanes running from the switches to unused slots may be identified, and the unused switch ports corresponding to the unused switch fabric bus lanes may be disabled. During a subsequent bus enumeration procedure for the switch fabric bus, bus numbers may be allocated to the identified used switch ports (or corresponding used slots) but not to the identified unused switch ports (or corresponding unused slots). The link training, used/unused switch port identification, and bus enumeration may all be performed each time the chassis is reset.
1. A processor configured to:
determine that first switch ports of a plurality of switch ports are disabled, wherein the first switch ports have been disabled because they are routed to unused slots of a plurality of slots via corresponding first bus lanes of a switch fabric bus, wherein the plurality of slots are configured to couple devices to the switch fabric bus;
determine that second switch ports of the plurality of switch ports are not disabled, wherein the second switch ports have not been disabled because they are routed to used slots of the plurality of slots via corresponding second bus lanes of the switch fabric bus; and
allocate bus numbers to the second switch ports but not to the first switch ports at least partially in response to determining that the first switch ports are disabled and the second switch ports are not disabled.
2. The processor of claim 1 , wherein the switch ports are included in one or more switches that interface the plurality of slots with the switch fabric bus.
3. The processor of claim 1 , further configured to:
determine that the first switch ports are routed to the unused slots and the second switch ports are routed to the used slots based at least in part on a link training procedure performed to link-train one or more switches with the plurality of slots, wherein the one or more switches include the plurality of switch ports.
4. The processor of claim 3 , further configured to:
query the one or more switches to obtain information indicative of results of the link training procedure; and
determine that the first switch ports are routed to the unused slots and the second switch ports are routed to the used slots further based on the obtained information.
5. The processor of claim 3 , further configured to:
disable the first switch ports at least partially in response to determining that the first switch ports are routed to the unused slots.
6. The processor of claim 1 , further configured to allocate the bus numbers and determine that the first switch ports are routed to the unused slots and the second switch ports are routed to the used slots as part of a bus enumeration procedure for the switch fabric bus.
7. The processor of claim 1 , wherein the switch fabric bus includes one or more of:
a peripheral component interconnect express (PCIe) bus; or
a PCIe extensions for instrumentation (PXIe) bus.
8. The processor of claim 1 , wherein the plurality of slots are part of a chassis configured to contain the devices.
9. A chassis comprising:
a plurality of slots configured to couple devices to a switch fabric bus;
a plurality of switch ports corresponding to respective bus lanes of the switch fabric bus; and
a control unit communicatively coupled to the plurality of switch ports and configured to:
determine that first switch ports of the plurality of switch ports are disabled, wherein the first switch ports have been disabled because they are routed to unused slots of a plurality of slots via corresponding first bus lanes of the respective bus lanes;
determine that second switch ports of the plurality of switch ports are not disabled, wherein the second switch ports have not been disabled because they are routed to used slots of the plurality of slots via corresponding second bus lanes of the respective bus lanes; and
allocate bus numbers to the second switch ports but not to the first switch ports at least partially in response to determining that the first switch ports are disabled and the second switch ports are not disabled.
10. The chassis of claim 9 , wherein the control unit is further configured to:
determine that the first switch ports are routed to the unused slots and the second switch ports are routed to the used slots based at least in part on a link training procedure performed to link-train one or more switches with the plurality of slots, wherein the one or more switches include the plurality of switch ports.
11. The chassis of claim 10 , wherein the control unit is further configured to:
query the one or more switches to obtain information indicative of results of the link training procedure; and
determine that the first switch ports are routed to the unused slots and the second switch ports are routed to the used slots further based on the obtained information.
12. The chassis of claim 10 , wherein the control unit is further configured to:
disable the first switch ports at least partially in response to determining that the first switch ports are routed to the unused slots.
13. The chassis of claim 9 , wherein the switch fabric bus includes one or more of:
a peripheral component interconnect express (PCIe) bus; or
a PCIe extensions for instrumentation (PXIe) bus.
14. The chassis of claim 9 , further comprising:
one or more switch fabric bus bridges, each switch fabric bus bridge coupled to a corresponding switch port of the plurality of switch ports;
wherein each slot of the plurality of slots includes a first electrical connection to a corresponding switch port of the plurality of switch ports and a second electrical connection to one of the one or more switch fabric bus bridges.
15. The chassis of claim 14 , wherein each of the one or more switch fabric bus bridges corresponds to multiple slots of the plurality of slots.
16. A non-transitory memory element storing instructions executable by a processor to:
determine that first switch ports of a plurality of switch ports are disabled, wherein the first switch ports have been disabled because they are routed to unused slots of a plurality of slots of a chassis via corresponding first bus lanes of a switch fabric bus, wherein the plurality of slots are configured to couple devices to the switch fabric bus;
determine that second switch ports of the plurality of switch ports are not disabled, wherein the second switch ports have not been disabled because they are routed to used slots of the plurality of slots of the chassis via corresponding second bus lanes of the switch fabric bus; and
allocate bus numbers to the second switch ports but not the first switch ports at least partially in response to determining that the first switch ports are disabled and the second switch ports are not disabled.
17. The non-transitory memory element of claim 16 , wherein the instructions are further executable by the processor to:
determine that the first switch ports are routed to the unused slots and the second switch ports are routed to the used slots based at least in part on a link training procedure performed to link-train one or more switches with the plurality of slots, wherein the one or more switches include the plurality of switch ports.
18. The non-transitory memory element of claim 17 , wherein the instructions are further executable by the processor to:
query the one or more switches to obtain information indicative of results of the link training procedure; and
determine that the first switch ports are routed to the unused slots and the second switch ports are routed to the used slots further based on the obtained information.
19. The non-transitory memory element of claim 16 , wherein the switch fabric bus includes one or more of:
a peripheral component interconnect express (PCIe) bus; or
a PCIe extensions for instrumentation (PXIe) bus.
20. The non-transitory memory element of claim 18 , wherein the instructions are further executable by the processor to disable the first switch ports at least partially in response to determining that the first switch ports are routed to the unused slots.